Tegra186: calculate proper power state for cluster/system power down

Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a c

Tegra186: calculate proper power state for cluster/system power down

Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a cluster power down.

This patch fixes this anomaly and sets the correct power state during a
cluster/system power down.

Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: max retries for ARI requests

This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.

Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signe

Tegra186: mce: max retries for ARI requests

This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.

Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memmap Tegra micro-seconds timer controller

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a8719

Tegra: memmap Tegra micro-seconds timer controller

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Control inclusion of helper code used for asserts

One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such co

Tegra: Control inclusion of helper code used for asserts

One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such code
so that it is based on the ENABLE_ASSERTIONS build option.

Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #912 from vwadekar/tegra-smmu-ctx-save-robust

Tegra: smmu: make the context save sequence robust

Tegra: smmu: make the context save sequence robust

This patch sanity checks the SMMU context created by the platform
code. The first entry contains the size of the array; which the
driver now verifi

Tegra: smmu: make the context save sequence robust

This patch sanity checks the SMMU context created by the platform
code. The first entry contains the size of the array; which the
driver now verifies before moving on with the save.

This patch also fixes an error in the calculation of the size of
the context that gets copied to TZDRAM.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: Support AARCH32/64 encoding for MCE calls

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads

Tegra186: Support AARCH32/64 encoding for MCE calls

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads. This patch supports MCE SMC functions ID for
AARCH32 and AARCH64 architectures to support such clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MI

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.

Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: Avoid implementation-defined bitfield types

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This pre

Tegra186: mce: Avoid implementation-defined bitfield types

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This prevents TF
from being built with such toolchains, since -Werror -pedantic options are
used.

gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a
warning in all cases required by the standard, but the standard does not
require a warning in this case.

See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773

Signed-off-by: Stephen Warren <swarren@nvidia.com>

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Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we suppor

Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we support multiple SMMUs.

Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Prite

Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: allow platforms to override plat_core_pos_by_mpidr()

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own

Tegra: allow platforms to override plat_core_pos_by_mpidr()

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own.

Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own
implementation of plat_core_pos_by_mpidr().

Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Control

Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Controller
driver. This allows the platforms to program the Memory Controller as per
their needs and makes the driver scalable.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: support for TEGRA_ARI_MISC_CCPLEX_EDBGREQ

This ARI call enables the EDBGREQ feature in the CCPLEX,
which will cause the CPUs to enter debug state instead of
vectoring to sw (ie MCA ha

Tegra186: mce: support for TEGRA_ARI_MISC_CCPLEX_EDBGREQ

This ARI call enables the EDBGREQ feature in the CCPLEX,
which will cause the CPUs to enter debug state instead of
vectoring to sw (ie MCA handler) upon receiving an async
abort signal.

Change-Id: Ifcb0e11446b6ac55179e3350d8f02b60ba32c94d
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: update t18x_ari.h to v3.1

This patch updates the ARI header file to v3.1.

Change-Id: I3e58cf50d27fb6e72062bb9d9782b75296b32025
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: PSCI: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: Ib67eda64b09f26fb2f427f0d624f05708

Tegra186: PSCI: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: Ib67eda64b09f26fb2f427f0d624f057081473132
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: config to enable SMMU device

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but f

Tegra: memctrl_v2: config to enable SMMU device

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but future platforms might not support it.

Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requi

Tegra186: read activity monitor's clock counter values

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: make AFI device settings configurable

This patch adds a new config to enable MC settings for the AFIW
and AFIR devices. Platforms must enable this config on their own.

Change-Id:

Tegra: memctrl_v2: make AFI device settings configurable

This patch adds a new config to enable MC settings for the AFIW
and AFIR devices. Platforms must enable this config on their own.

Change-Id: I53b450117e4764ea76d9347ee2928f9be178b107
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: move smmu driver to tegra/common

This patch moves the smmu driver introduced by the Tegra186 port
to tegra/common so that future chips can (re)use it.

Change-Id: Ia44c7f2a62fb2d8869db3a44

Tegra186: move smmu driver to tegra/common

This patch moves the smmu driver introduced by the Tegra186 port
to tegra/common so that future chips can (re)use it.

Change-Id: Ia44c7f2a62fb2d8869db3a44742a8c6b13c49036
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: split MCE driver into public/private interfaces

This patch splits the MCE driver into public and private interfaces
to allow usage of common functionality across multiple SoCs.

Change-Id:

Tegra186: split MCE driver into public/private interfaces

This patch splits the MCE driver into public and private interfaces
to allow usage of common functionality across multiple SoCs.

Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: move platform specific MCE defines to tegra_def.h

This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.

Change-Id: If8660c

Tegra186: move platform specific MCE defines to tegra_def.h

This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.

Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: use MSB of wake_time

This patch updates wake time of the cpu to use the MSBs and zero
out the LSB's. Only 24 out of 32 bits are currently passed
through the PSCI interface. Previously all

Tegra186: use MSB of wake_time

This patch updates wake time of the cpu to use the MSBs and zero
out the LSB's. Only 24 out of 32 bits are currently passed
through the PSCI interface. Previously all the LSB's were used.

Change-Id: Ie2d9d1bf6e3003dd47526a124f64e6ad555d2371
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: Update API for reset vector ARI

The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with
request_lo/hi set to zero. MTS automatically takes the reset
vector from MISCREG_AA64_RST regi

Tegra186: Update API for reset vector ARI

The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with
request_lo/hi set to zero. MTS automatically takes the reset
vector from MISCREG_AA64_RST register and does not need it to
be passed as parameters. This patch updates the API and the
caller function accordingly.

Change-Id: Ie3e3402d93951102239d988ca9f0cdf94f290d2f
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: clean CPU wake times from L2 cache

When entering C7, ATF disables caches and flushes the L1 cache. However,
wake_time[cpu] can still remain in the L2 cache, causing later reads to it
to fe

Tegra186: clean CPU wake times from L2 cache

When entering C7, ATF disables caches and flushes the L1 cache. However,
wake_time[cpu] can still remain in the L2 cache, causing later reads to it
to fetch from DRAM. This will read stale values.

Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it
before disabling caches.

Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311
Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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