| 2e446f50 | 29-Apr-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: sip_calls: mark unused parameter as const
This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.
Change-Id
Tegra194: sip_calls: mark unused parameter as const
This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.
Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 42de0384 | 28-Apr-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: implement handler to retrieve power domain tree
This patch implements the platform handler to return the pointer
to the power domain tree.
Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc
Tegra194: implement handler to retrieve power domain tree
This patch implements the platform handler to return the pointer
to the power domain tree.
Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 73dad7f9 | 28-Apr-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra194: mce: fix function declaration conflicts
To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.
Change-Id: I09e96a1874dd86626c7e41c92a1484a84e38740
Tegra194: mce: fix function declaration conflicts
To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.
Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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| 5da8ec56 | 10-Apr-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Tegra194: skip notifying MCE in fake system suspend
- In pre-silicon platforms, MCE might not be ready
to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
MCE'
Tegra194: skip notifying MCE in fake system suspend
- In pre-silicon platforms, MCE might not be ready
to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
MCE's acknowledgment to enter system suspend
Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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| ddbf946f | 20-Mar-2017 |
Stefan Kristiansson <stefank@nvidia.com> |
Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.
Ch
Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.
Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
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| 4fb71eae | 03-Mar-2017 |
Rohit Khanna <rokhanna@nvidia.com> |
Tegra194: Dont run MCE firmware on Emulation
Dont run MCE firmware on pre-silicon emulation platforms
Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvid
Tegra194: Dont run MCE firmware on Emulation
Dont run MCE firmware on pre-silicon emulation platforms
Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
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| e9bb627d | 13-Feb-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: remove GPU, MPCORE and PTC registers from streamid list
GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.
Change-Id: I14b450a11f02ad6c1a9
Tegra194: remove GPU, MPCORE and PTC registers from streamid list
GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.
Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| 7e4ffcd9 | 22-Feb-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: Support SMC64 encoding for MCE calls
This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.
Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-of
Tegra194: Support SMC64 encoding for MCE calls
This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.
Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 2ac8cb7e | 02-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: add SMMU and mc_sid support
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to
Tegra194: add SMMU and mc_sid support
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.
Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| d11c793b | 23-Dec-2016 |
Steven Kao <skao@nvidia.com> |
Tegra194: psci: support for 64-bit TZDRAM base
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f335
Tegra194: psci: support for 64-bit TZDRAM base
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 5e2fe3a3 | 11-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: trampoline: include bl_common.h
This patch includes bl_common.h from plat_trampoline.S to link with
the __BL31_END__ symbol.
Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73
Signed-of
Tegra186: trampoline: include bl_common.h
This patch includes bl_common.h from plat_trampoline.S to link with
the __BL31_END__ symbol.
Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 9a861d0f | 25-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: remove ENABLE_AFI_DEVICE macro usage
This patch removes this macro and its usage as it is used only
within the Tegra186 files and all derived platforms keep the
macro enabled.
Change-Id:
Tegra186: remove ENABLE_AFI_DEVICE macro usage
This patch removes this macro and its usage as it is used only
within the Tegra186 files and all derived platforms keep the
macro enabled.
Change-Id: Ib831b3c002ba4dedc3d5fafbb7d321daa28fa9ea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 15440c52 | 03-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
spd: trusty: memmap trusty's code memory before peeking
This patch dynamically maps the first page of trusty's code memory,
before accessing it to find out if we are running a 32-bit or 64-bit
image
spd: trusty: memmap trusty's code memory before peeking
This patch dynamically maps the first page of trusty's code memory,
before accessing it to find out if we are running a 32-bit or 64-bit
image.
On Tegra platforms, this means we have to increase the mappings to
accomodate the new memmap entry.
Change-Id: If370d1e6cfcccd69b260134c1b462d8d17bee03d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a01b0f16 | 12-Mar-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: restrict non-secure PMC accesses
Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always acc
Tegra: restrict non-secure PMC accesses
Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always access the PMC through the EL3
exception space.
This patch restricts non-secure world access to the PMC block on
such platforms.
Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a7f4e89b | 07-Dec-2017 |
Krishna Reddy <vdumpa@nvidia.com> |
Tegra186: memctrl: disable stream id writes for MC clients
As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patc
Tegra186: memctrl: disable stream id writes for MC clients
As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patch
disables stream id register writes for these MC clients to implement
those recommendations.
Change-Id: I8887c0f2cc5bc3fc5bba42074810ba5c1d3f121f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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| 6a397d1d | 20-Apr-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra210: toggle ring oscillator across cluster idle
This patch toggles the ring oscillator state across cluster idle
as DFLL loses its state. We dont want garbage values being written
to the pmic w
Tegra210: toggle ring oscillator across cluster idle
This patch toggles the ring oscillator state across cluster idle
as DFLL loses its state. We dont want garbage values being written
to the pmic when we enter cluster idle state, so enable "open loop"
when we enter CC6 and restore the state to "closed loop" on exit.
Change-Id: I56f4649f57bcc651d6c415a6dcdc978e9444c97b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| da0f4743 | 09-Apr-2018 |
kalyani chidambaram <kalyanic@nvidia.com> |
Tegra210: clear PMC_DPD registers on resume
This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.
Change-Id: I7881ef0a5
Tegra210: clear PMC_DPD registers on resume
This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.
Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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