| #
65012c08 |
| 10-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "tegra-downstream-02182020" into integration
* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegr
Merge changes from topic "tegra-downstream-02182020" into integration
* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegra186: add support for bpmp_ipc driver
Tegra210: disable ERRATA_A57_829520
Tegra194: memctrl: add support for MIU4 and MIU5
Tegra194: memctrl: remove support to reconfigure MSS
Tegra: fiq_glue: remove bakery locks from interrupt handler
Tegra210: SE: add context save support
Tegra210: update the PMC blacklisted registers
Tegra: disable CPUACTLR access from lower exception levels
cpus: denver: fixup register used to store return address
show more ...
|
| #
41554fb2 |
| 10-Apr-2018 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra210: SE: add context save support
Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based sa
Tegra210: SE: add context save support
Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based save/restore mechanism
instead.
This patch updates the SE driver to make this change.
Change-Id: Ia5e5ed75d0fe011f17809684bbc2ed2338925946
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
show more ...
|
| #
13be0ee4 |
| 10-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration
|
| #
f1f72019 |
| 09-Jan-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
plat: nvidia: remove spurious UTF-8 characters at top of platform files
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423
|
| #
c40c88f8 |
| 21-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19
Tf2.0 tegra downstream rebase 1.7.19
|
| #
5ed1755a |
| 11-Apr-2017 |
Marvin Hsu <marvinh@nvidia.com> |
Tegra210B01: SE/SE2 and PKA1 context save (SW)
This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save
Tegra210B01: SE/SE2 and PKA1 context save (SW)
This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.
Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
show more ...
|
| #
aa64c5fb |
| 26-Jul-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: fix defects flagged by MISRA Rule 10.3
MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.
Tegra: fix defects flagged by MISRA Rule 10.3
MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.
The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.
Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.
Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
show more ...
|
| #
af4aad2f |
| 17-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1733 from vwadekar/tf2.0-tegra-downstream-rebase-1.3.19
Tegra downstream rebase 1.3.19
|
| #
8668fe0c |
| 15-May-2017 |
Sam Payne <spayne@nvidia.com> |
Tegra210B01: initialize DRBG on boot and resume
DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume fo
Tegra210B01: initialize DRBG on boot and resume
DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume for SE1 and SE2. This SRK
value is not saved to PMC scratch, and should be overwitten
during atomic suspend.
Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c
Signed-off-by: Sam Payne <spayne@nvidia.com>
show more ...
|
| #
ce3c97c9 |
| 11-Apr-2017 |
Marvin Hsu <marvinh@nvidia.com> |
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.
Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|