Tegra194: Update t194_nvg.h to v6.7

This patch updates the t194_nvg.h header file received from the CPU
team to v6.7.

Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774
Signed-off-by: Kalyani Chi

Tegra194: Update t194_nvg.h to v6.7

This patch updates the t194_nvg.h header file received from the CPU
team to v6.7.

Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS

Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, wa

Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: memctrl: lock some more MC SID security configs

The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to

Tegra194: memctrl: lock some more MC SID security configs

The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to the list. Since the reset value of these registers
is already as per expectations, there is no need to change it.

MC SID security configs
- PTCR,
- MIU6R, MIU6W, MIU7R, MIU7W,
- MPCORER, MPCOREW,
- NVDEC1SRD, NVDEC1SRD1, NVDEC1SWR.

Change-Id: Ia9a1f6a6b6d34fb2787298651f7a4792a40b88ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
s

Tegra194: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.

Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra194: store TZDRAM base/size to scratch registers

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify in

Tegra194: store TZDRAM base/size to scratch registers

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra194: fix warnings for extra parentheses

armclang displays warnings for extra parentheses, leading to
build failures as warnings are treated as errors.
This patch removes the extra parentheses t

Tegra194: fix warnings for extra parentheses

armclang displays warnings for extra parentheses, leading to
build failures as warnings are treated as errors.
This patch removes the extra parentheses to fix this issue.

Change-Id: Id2fd6a3086590436eecabc55502f40752a018131
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra194: memctrl: add support for MIU4 and MIU5

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to

Tegra194: memctrl: add support for MIU4 and MIU5

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to miu5
support is provided.

Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
Signed-off-by: Pravin <pt@nvidia.com>

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Tegra194: memctrl: remove support to reconfigure MSS

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there

Tegra194: memctrl: remove support to reconfigure MSS

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there is a chance that bpmp-fw is
trying to perform accesses while the hot flush is active.

Therefore, the mss client reconfigure has been moved to
System Suspend resume fw and bootloader, and it can be
removed from here.

Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>

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spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data struct

spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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LS 16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data s

LS 16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: Ifd6aff1064ba1c3c029cdd8a83f715f7a9976db5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data stru

16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the

Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: memctrl: lock mc stream id security config

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the fol

Tegra194: memctrl: lock mc stream id security config

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.

- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW

Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: mce: declare nvg_roc_clean_cache_trbits()

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

C

Tegra194: mce: declare nvg_roc_clean_cache_trbits()

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

Change-Id: I313556f6799792fc0141afb5822cc157db80bc47
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: remove support for simulated system suspend

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now

Tegra194: remove support for simulated system suspend

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.

Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: fix multiple MISRA issues

This patch fixes violations of the following MISRA rules

* Rule 8.5 "An external object or function shall be declared once in
one and only one

Tegra194: mce: fix multiple MISRA issues

This patch fixes violations of the following MISRA rules

* Rule 8.5 "An external object or function shall be declared once in
one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
object with a narrower essential type or of a different
esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: se: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 8.4 "A compatible declaration shall be visible when an object or
function with

Tegra194: se: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 8.4 "A compatible declaration shall be visible when an object or
function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
conversions are perdormed shall have the same essential type
category"
* Rule 17.7 "The value returned by a function having non-void return
type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove weakly defined PSCI platform handlers

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-I

Tegra: remove weakly defined PSCI platform handlers

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently,

Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Tegra194: enable spe-console functionality

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: V

Tegra194: enable spe-console functionality

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: remove unused NVG functions

This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_d

Tegra194: mce: remove unused NVG functions

This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_disable_power_saver_modes
* nvg_roc_clean_cache
* nvg_roc_flush_cache

Change-Id: I0387a40dec35686deaad623a8350de89acfe9393
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: support for NVG interface v6.6

This patch updates the NVG interface header file to v6.6.

Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f
Signed-off-by: Varun Wadekar <vwadekar@nvidia

Tegra194: support for NVG interface v6.6

This patch updates the NVG interface header file to v6.6.

Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list

PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
D

Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list

PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
Due to addition of above registers, increasing context save memory
by 2 bytes.

Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: enable driver for general purpose DMA engine

This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.

Change-Id: I8cbec99be6ebe4da742212

Tegra194: enable driver for general purpose DMA engine

This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.

Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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