Tegra186: add support for bpmp_ipc driver

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818a

Tegra186: add support for bpmp_ipc driver

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data stru

16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the

Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform handler to relocate BL32 image

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZD

Tegra: platform handler to relocate BL32 image

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c96

Tegra186: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c9679602ecb47b53
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: memctrl: lock stream id security config

Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-b

Tegra186: memctrl: lock stream id security config

Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: remove weakly defined PSCI platform handlers

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-I

Tegra: remove weakly defined PSCI platform handlers

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove weakly defined platform setup handlers

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some M

Tegra: remove weakly defined platform setup handlers

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: introduce plat_enable_console()

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while a

Tegra: introduce plat_enable_console()

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: trampoline: include bl_common.h

This patch includes bl_common.h from plat_trampoline.S to link with
the __BL31_END__ symbol.

Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73
Signed-of

Tegra186: trampoline: include bl_common.h

This patch includes bl_common.h from plat_trampoline.S to link with
the __BL31_END__ symbol.

Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: use common 'BL31_BASE' variable

This patch modfies the 'tegra_soc_pwr_domain_power_down_wfi' handler
to use BL31_BASE variable, provided by bl_common.h

Change-Id: I9747228d0193c1ae6999284

Tegra186: use common 'BL31_BASE' variable

This patch modfies the 'tegra_soc_pwr_domain_power_down_wfi' handler
to use BL31_BASE variable, provided by bl_common.h

Change-Id: I9747228d0193c1ae6999284458b9f866955a61a2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: remove ENABLE_AFI_DEVICE macro usage

This patch removes this macro and its usage as it is used only
within the Tegra186 files and all derived platforms keep the
macro enabled.

Change-Id:

Tegra186: remove ENABLE_AFI_DEVICE macro usage

This patch removes this macro and its usage as it is used only
within the Tegra186 files and all derived platforms keep the
macro enabled.

Change-Id: Ib831b3c002ba4dedc3d5fafbb7d321daa28fa9ea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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spd: trusty: memmap trusty's code memory before peeking

This patch dynamically maps the first page of trusty's code memory,
before accessing it to find out if we are running a 32-bit or 64-bit
image

spd: trusty: memmap trusty's code memory before peeking

This patch dynamically maps the first page of trusty's code memory,
before accessing it to find out if we are running a 32-bit or 64-bit
image.

On Tegra platforms, this means we have to increase the mappings to
accomodate the new memmap entry.

Change-Id: If370d1e6cfcccd69b260134c1b462d8d17bee03d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: initialise per-CPU GIC interface(s)

This patch initilises the per-CPU GIC bits during cold boot and
secondary CPU power up. Commit 80c50ee accidentally left out this
part.

Change-Id: I73ce59

Tegra: initialise per-CPU GIC interface(s)

This patch initilises the per-CPU GIC bits during cold boot and
secondary CPU power up. Commit 80c50ee accidentally left out this
part.

Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: memctrl: disable stream id writes for MC clients

As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patc

Tegra186: memctrl: disable stream id writes for MC clients

As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patch
disables stream id register writes for these MC clients to implement
those recommendations.

Change-Id: I8887c0f2cc5bc3fc5bba42074810ba5c1d3f121f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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Tegra: organize memory/mmio apertures to decrease memmap latency

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been mo

Tegra: organize memory/mmio apertures to decrease memmap latency

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.

Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: smmu: add support for backup multiple smmu regs

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs t

Tegra186: smmu: add support for backup multiple smmu regs

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs that can be used for multiple
smmus.

Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra186: remove RELOCATE_TO_BL31_BASE config

This patch removes this unused config option from the Tegra186
platform makefiles.

Change-Id: Idcdf6854332a26599323a247289c2d3ce19f475f
Signed-off-by:

Tegra186: remove RELOCATE_TO_BL31_BASE config

This patch removes this unused config option from the Tegra186
platform makefiles.

Change-Id: Idcdf6854332a26599323a247289c2d3ce19f475f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config

This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.

Change-Id: Ie7adb641adeb36

Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config

This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.

Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: console driver compilation from platform makefiles

This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms

Tegra: console driver compilation from platform makefiles

This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.

Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: platform handler for TZDRAM setup

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to

Tegra: memctrl_v2: platform handler for TZDRAM setup

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.

Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra186: save system suspend entry marker to TZDRAM

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is

Tegra186: save system suspend entry marker to TZDRAM

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra186 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: helper functions for CPU rst handler and SMMU ctx offset

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offse

Tegra186: helper functions for CPU rst handler and SMMU ctx offset

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: rename secure scratch register macros

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* ->

Tegra: rename secure scratch register macros

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: memctrl_v2: platform handler for TZDRAM settings

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers

Tegra: memctrl_v2: platform handler for TZDRAM settings

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.

Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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