| e44f86ef | 17-May-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: remove weakly defined PSCI platform handlers
This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.
Change-I
Tegra: remove weakly defined PSCI platform handlers
This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.
Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 5f1803f9 | 15-May-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: per-SoC DRAM base values
Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC header
Tegra: per-SoC DRAM base values
Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.
Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 4a9026d4 | 03-Apr-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: enable driver for general purpose DMA engine
This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.
Change-Id: I8cbec99be6ebe4da742212
Tegra194: enable driver for general purpose DMA engine
This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.
Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| ceb12020 | 23-Jan-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: organize the memory/mmio map to make it linear
This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it eas
Tegra194: organize the memory/mmio map to make it linear
This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it easier for the xlat_tables_v2 library to create mappings for each
mmap_add_region call.
Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 33a8ba6a | 09-Feb-2018 |
Steven Kao <skao@nvidia.com> |
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure s
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.
This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.
Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address
Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 34a6610a | 07-Mar-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: set reorder depth limit for PCIE blocks
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
S
Tegra194: memctrl: set reorder depth limit for PCIE blocks
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.
Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
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| 1296da6d | 05-Jan-2018 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
m
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.
For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.
This change sets all these MC registers as per HW spec file.
Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a0cacc95 | 18-Jan-2018 |
Arto Merilainen <amerilainen@nvidia.com> |
Tegra194: memctrl: Disable PVARDC coalescer
Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0
Tegra194: memctrl: Disable PVARDC coalescer
Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.
Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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| d11f5e05 | 03-Jan-2018 |
steven kao <skao@nvidia.com> |
Tegra194: toggle SE clock during context save/restore
This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called
Tegra194: toggle SE clock during context save/restore
This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.
Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>
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| 221b8e57 | 23-Dec-2017 |
Krishna Reddy <vdumpa@nvidia.com> |
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't us
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't use coherent
path and stage-2 smmu mappings won't mark transactions as non-coherent.
For native case, no-override works. But, not for virtualization case.
Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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| 95f68bc4 | 18-Dec-2017 |
Krishna Reddy <vdumpa@nvidia.com> |
Tegra194: memctrl: fix bug in client order id reg value generation
Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always ze
Tegra194: memctrl: fix bug in client order id reg value generation
Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always zero. Updated mc_client_order_id macro to avoid and'ing outside
the macro, to take the reg value and update specific bit field
as necessary.
Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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| c766adce | 19-Dec-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: memctrl: enable mc coalescer
This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.
Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb
Tegra194: memctrl: enable mc coalescer
This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.
Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| f3ec5c0c | 24-Dec-2017 |
steven kao <skao@nvidia.com> |
Tegra194: update scratch registers used to read boot parameters
This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81
instead of SECURE_SCRATCH_RSV44. The previous level boot
Tegra194: update scratch registers used to read boot parameters
This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81
instead of SECURE_SCRATCH_RSV44. The previous level bootloader changed this
setting, so update here to keep both components in sync.
Change-Id: I4e0c1b54fc69482d5513a8608d0bf616677e1bdd
Signed-off-by: steven kao <skao@nvidia.com>
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| 67db3231 | 09-Jan-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: include: fix violations of MISRA Rule 21.1
This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
Tegra: include: fix violations of MISRA Rule 21.1
This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
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| 13be0ee4 | 10-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration |
| f1f72019 | 09-Jan-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
plat: nvidia: remove spurious UTF-8 characters at top of platform files
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423 |
| 7a05f06a | 02-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by:
Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 8ecc4291 | 15-Dec-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: introduce tegra_mc_def.h
This patch introduces memory controller register defines
for Tegra194 platforms.
Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raith
Tegra194: introduce tegra_mc_def.h
This patch introduces memory controller register defines
for Tegra194 platforms.
Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| 56c27438 | 09-Feb-2018 |
Steven Kao <skao@nvidia.com> |
Tegra194: 40-bit wide memory address space
This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.
Change-Id: Ie1bcdec2c4e8e15975048ce1c2a3
Tegra194: 40-bit wide memory address space
This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.
Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 2d1f1010 | 22-Jan-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra194: add support to reset GPU
This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.
Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by:
Tegra194: add support to reset GPU
This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.
Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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| 95397d96 | 30-Nov-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: memctrl: fix logic to check TZDRAM config register access
This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The pola
Tegra194: memctrl: fix logic to check TZDRAM config register access
This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.
Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 117dbe6c | 21-Aug-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: introduce plat_enable_console()
This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while a
Tegra: introduce plat_enable_console()
This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.
For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.
Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| f0222c23 | 21-Aug-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: include: drivers: introduce spe.h
This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.
S
Tegra: include: drivers: introduce spe.h
This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799
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| 4e697b77 | 14-Nov-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: memctrl: platform handler for TZDRAM setup
This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers
Tegra194: memctrl: platform handler for TZDRAM setup
This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.
Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 040529e9 | 10-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: save system suspend entry marker to TZDRAM
This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is
Tegra194: save system suspend entry marker to TZDRAM
This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.
The Tegra194 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.
Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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