| 420c26b3 | 28-Sep-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
fix(plat/mediatek/mt8183): fix out-of-bound access
Fix coverity checks which is found on:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1806/comment/eaec126f_af5eb624/
Change-Id: I
fix(plat/mediatek/mt8183): fix out-of-bound access
Fix coverity checks which is found on:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1806/comment/eaec126f_af5eb624/
Change-Id: I9405f7f67aa4115c1a7b8b4623b6b0830e62f814
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| b3b162f3 | 28-Sep-2021 |
Pan Gao <gtk_pangao@mediatek.com> |
feat(plat/mediatek/common): enable software reset for CIRQ
CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.
BUG=b:1922
feat(plat/mediatek/common): enable software reset for CIRQ
CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.
BUG=b:192200380, b:201035723
Signed-off-by: Pan Gao <gtk_pangao@mediatek.com>
Change-Id: Id53ea099ae566bf2a573fca866bd10c60429bd5a
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| 3b994a75 | 10-Aug-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
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| 85e4d14d | 17-Sep-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8195): fix coverity fail
Add break to correct the driver flow.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie20f402d543fbf90172671e007fad30d5dc2ab10 |
| 75edd34a | 19-Aug-2021 |
Penny Jan <penny.jan@mediatek.com> |
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.
Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
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| d562130e | 09-Jul-2021 |
Dawei Chien <dawei.chien@mediatek.com> |
feat(plat/mediatek/mt8195): add vcore-dvfs support
Add DVFSRC init flow.
Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> |
| 5183e637 | 05-Jul-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
feat(plat/mdeiatek/mt8192): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those
feat(plat/mdeiatek/mt8192): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9c7af9a4f75216ed2c6b44458d121a352bef4b95
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| 310c3a26 | 24-Jun-2021 |
Roger Lu <roger.lu@mediatek.com> |
fix(mediatek/mt8192/spm): add missing bit define for debug purpose
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6dbf6d4ea6310c3371ca15d1e7cce249a05af2fb |
| 1f81ccce | 20-Jul-2021 |
Garmin Chang <garmin.chang@mediatek.com> |
fix(plat/mediatek/me8195): fix error setting for SPM
There is a error setting for SPM, so we need to fix this issue.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a
fix(plat/mediatek/me8195): fix error setting for SPM
There is a error setting for SPM, so we need to fix this issue.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57
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| 49d3bd8c | 02-Jul-2021 |
Garmin Chang <garmin.chang@mediatek.com> |
feat(plat/mediatek/mt8195): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable M
feat(plat/mediatek/mt8195): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
Change-Id: I3237199bc217bd3682f51d31284db5fd0324b396
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
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| 859e346b | 28-Jun-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8195): add SPM suspend driver
Support DRAM/MAINPLL/26M off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib850
feat(plat/mediatek/mt8195): add SPM suspend driver
Support DRAM/MAINPLL/26M off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77
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| d336e093 | 28-Jun-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
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| 04818963 | 20-Jun-2021 |
Elly Chiang <elly.chiang@mediatek.com> |
feat(plat/mediatek/mt8195): add support for PTP3
Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.
Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Ell
feat(plat/mediatek/mt8195): add support for PTP3
Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.
Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Elly Chiang <elly.chiang@mediatek.com>
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| 9ff8b8ca | 18-Jun-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
fix(plat/mediatek/mt8195): extend MMU region size
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8195): extend MMU region size
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8195 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
Change-Id: I3a186ed71d0d963b59ae55e27a6d27a01fe4f638
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| 2a008779 | 16-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
fea
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
refactor(plat/st): export functions to get SoC information
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
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| b085b990 | 09-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(plat/mediatek/mpu): add MPU support for DSP" into integration |
| fb88c71d | 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/mdeiatek/mt8195): add display port control in SiP service" into integration |
| 6c4973b0 | 28-Apr-2021 |
Jiaxin Yu <jiaxin.yu@mediatek.com> |
feat(plat/mediatek/mpu): add MPU support for DSP
Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765
feat(plat/mediatek/mpu): add MPU support for DSP
Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765fd110d9009
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| 0f7d2e89 | 27-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/mediatek/pmic_wrap): update idle flow" into integration |
| 48648c09 | 20-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(plat/mediatek): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie1dbc54569086f6a74206b873f
refactor(plat/mediatek): use SOC_ID defines
Use the macros that are now defined in include/lib/smccc.h.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie1dbc54569086f6a74206b873fee664b4cdeea36
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| 9ed4e6fb | 05-May-2021 |
Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> |
fix(plat/mediatek/pmic_wrap): update idle flow
Update idle flow in case of last read command timeout.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Idb0552d70d59b23822c
fix(plat/mediatek/pmic_wrap): update idle flow
Update idle flow in case of last read command timeout.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Idb0552d70d59b23822c38269d0fa9fe9ac0d6975
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| f46e1f18 | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8192 APU device apc driver
Add APU device apc driver and setup permission.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I2bbdb69d11267e4252b2138b5c5ac8f
feat(plat/mediatek/apu): add mt8192 APU device apc driver
Add APU device apc driver and setup permission.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I2bbdb69d11267e4252b2138b5c5ac8faf752740f
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| ca4c0c2e | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8192 APU SiP call support
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ibf93d8ccf22c414de3093cee9e13f766858
feat(plat/mediatek/apu): add mt8192 APU SiP call support
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ibf93d8ccf22c414de3093cee9e13f7668588f69e
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@mediatek.com>
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| 7eb42237 | 12-Apr-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.c
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
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| 2671f318 | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8192 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
devapc control wrapper.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ie8e6a197c0
feat(plat/mediatek/apu): add mt8192 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
devapc control wrapper.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ie8e6a197c0f440f9e4ee8101202283a2dbf501a6
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