| fc8dc499 | 24-Oct-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: a3k: rename the UART images archive
Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot out
plat: marvell: armada: a3k: rename the UART images archive
Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot output folder upon flash image build.
Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 270367fb | 27-Aug-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: a3k: allow image load to RAM address 0
Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking th
plat: marvell: armada: a3k: allow image load to RAM address 0
Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.
Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| ff9cfdc0 | 21-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: comphy: cp110: add support for USB comphy polarity invert
The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't re
marvell: comphy: cp110: add support for USB comphy polarity invert
The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.
Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 38f6daca | 21-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: comphy: cp110: add support for SATA comphy polarity invert
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doe
marvell: comphy: cp110: add support for SATA comphy polarity invert
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.
Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 6792ba15 | 24-Jun-2019 |
Stefan Chulski <stefanc@marvell.com> |
plat: marvell: ap806: implement workaround for errata-id FE-4265711
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading
CNTVAL reflects the global system counter value in binary format.
Due to this er
plat: marvell: ap806: implement workaround for errata-id FE-4265711
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading
CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.
Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.
Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| 8f09da46 | 10-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: updat
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: update build instructions with CN913x
plat: marvell: octeontx: add support for t9130
plat: marvell: t9130: add SVC support
plat: marvell: t9130: update AVS settings
plat: marvell: t9130: pass actual CP count for load_image
plat: marvell: armada: a7k: add support to SVC validation mode
plat: marvell: armada: add support for twin-die combined memory device
show more ...
|
| 29214e95 | 30-Jul-2020 |
Grant Likely <grant.likely@arm.com> |
Use abspath to dereference $BUILD_BASE
If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is
Use abspath to dereference $BUILD_BASE
If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE))
to rationalize to an absolute path every time and remove the relative
path assumptions.
This patch also adds documentation that BUILD_BASE can be specified by
the user.
Signed-off-by: Grant Likely <grant.likely@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
show more ...
|
| 12c66c6b | 06-May-2019 |
Alex Evraev <alexev@marvell.com> |
plat: marvell: t9130: add SVC support
As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.
Chan
plat: marvell: t9130: add SVC support
As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.
Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3
Signed-off-by: Alex Evraev <alexev@marvell.com>
show more ...
|
| 885cd821 | 24-Jan-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: t9130: update AVS settings
Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.
Change-Id: Ib1dd70885a316ed5763d0f4730d0e47
plat: marvell: t9130: update AVS settings
Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.
Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 5bc3643e | 27-Mar-2019 |
Ben Peled <bpeled@marvell.com> |
plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.
Cha
plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.
Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9
Signed-off-by: Ben Peled <bpeled@marvell.com>
show more ...
|
| ebf307bf | 11-Aug-2019 |
Alex Evraev <alexev@marvell.com> |
plat: marvell: armada: a7k: add support to SVC validation mode
Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz
Change-Id: Ia72b10e0ccfad0756
plat: marvell: armada: a7k: add support to SVC validation mode
Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz
Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2
Signed-off-by: Alex Evraev <alexev@marvell.com>
show more ...
|
| 48270689 | 06-Oct-2019 |
Moti Buskila <motib@marvell.com> |
plat: marvell: armada: add support for twin-die combined memory device
the twin-die combined memory device should be treated as
X8 device and not as X16 one. This patch is required to
re-enable comp
plat: marvell: armada: add support for twin-die combined memory device
the twin-die combined memory device should be treated as
X8 device and not as X16 one. This patch is required to
re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade.
Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97
Signed-off-by: Moti Buskila <motib@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| 07678ff7 | 21-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I0826ef8b,I9b4659a1 into integration
* changes:
plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD
Merge changes I0826ef8b,I9b4659a1 into integration
* changes:
plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
show more ...
|
| a5de4319 | 10-Jun-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: armada: mcbin: squash several IO windows into one
There is no need to open tree different IO window when there is
possibility of having one covering required range.
Change-Id: I9feae
plat: marvell: armada: mcbin: squash several IO windows into one
There is no need to open tree different IO window when there is
possibility of having one covering required range.
Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 41e8c6fc | 13-Nov-2019 |
Marcin Wojtas <mw@semihalf.com> |
plat: marvell: armada: fix BL32 extra parameters usage
Update missing code releated to the BL32 payload.
Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semiha
plat: marvell: armada: fix BL32 extra parameters usage
Update missing code releated to the BL32 payload.
Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| 0a977b9b | 15-Apr-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
unt
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)
Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 0eb3d1fc | 15-Apr-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.
Change-Id: If8edeeec5861b52
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.
Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 0081cdd1 | 17-Apr-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: armada: move mg conf related code to appropriate driver
Now when mg_conf_cm3 driver is present - move all relevant code there.
Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Si
plat: marvell: armada: move mg conf related code to appropriate driver
Now when mg_conf_cm3 driver is present - move all relevant code there.
Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 9b883673 | 12-Apr-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: mg_conf_cm3: add basic driver
Implement function which will allow to start AP FW.
Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semiha
drivers: marvell: mg_conf_cm3: add basic driver
Implement function which will allow to start AP FW.
Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| 70ec0d72 | 04-Dec-2019 |
Luka Kovacic <luka.kovacic@sartura.hr> |
plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.
It supports 1 x 288-pin DIMM, DDR4 2400M
plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board
Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.
It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC).
The iEi Puzzle-M801 board is using a custom MCU to handle board
power management. The MCU is managing the boards power LEDs, fans
and some other periferals. It's using UART for communication.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8
show more ...
|
| 148798cd | 03-Jul-2020 |
Luka Kovacic <luka.kovacic@sartura.hr> |
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.
plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.
The variable was not updated, when it was deprecated in a8k_common.mk
in commit 613bbde09e48874658af5a00612fe2a0b0388523.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8
show more ...
|
| 47d1773f | 15-Apr-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.
Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Kon
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.
Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 5a40d70f | 31-Mar-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
drivers: marvell: add support for mapping the entire LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - d
drivers: marvell: add support for mapping the entire LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.
Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 85440805 | 31-Mar-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges
Change-Id
plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges
Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
show more ...
|
| 94d6f483 | 19-Jun-2020 |
Marcin Wojtas <mw@semihalf.com> |
plat: marvell: armada: reduce memory size reserved for FIP image
It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.
Change-Id: I58a8ce4408a646fe1afd
plat: marvell: armada: reduce memory size reserved for FIP image
It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.
Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Extract from bigger commit]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|