| #
eeb77da6 |
| 06-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
plat: marvell: armada: a3k: allow image load to RAM address 0
marvell: comphy: cp110: add support for USB comphy polarity invert
marvell: comphy: cp110: add support for SATA comphy polarity invert
marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
drivers: marvell: mochi: Update AP incoming masters secure level
plat: marvell: armada: add ccu window for workaround errata-id 3033912
plat: marvell: ap806: implement workaround for errata-id FE-4265711
show more ...
|
| #
6792ba15 |
| 24-Jun-2019 |
Stefan Chulski <stefanc@marvell.com> |
plat: marvell: ap806: implement workaround for errata-id FE-4265711
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading
CNTVAL reflects the global system counter value in binary format.
Due to this er
plat: marvell: ap806: implement workaround for errata-id FE-4265711
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading
CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.
Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.
Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|
| #
9935047b |
| 17-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble:
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble: ap807: clean-up PLL configuration sequence
ddr: a80x0: add DDR 32-bit mode support
plat: marvell: mci: perform mci link tuning for all mci interfaces
plat: marvell: mci: use more meaningful name for mci link tuning
plat: marvell: a8k: remove wrong or unnecessary comments
plat: marvell: ap807: enable snoop filter for ap807
plat: marvell: ap807: update configuration space of each CP
plat: marvell: ap807: use correct address for MCIx4 register
plat: marvell: add support for PLL 2.2GHz mode
plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
marvell: armada: add extra level in marvell platform hierarchy
show more ...
|
| #
38a7e6cd |
| 23-Jan-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: ap807: enable snoop filter for ap807
Snoop filter needs to be enabled once per cluster.
Change-Id: I241e72f21982142ba290c7547df6f434e6a6a98d
Signed-off-by: Grzegorz Jaszczyk <jaz@sem
plat: marvell: ap807: enable snoop filter for ap807
Snoop filter needs to be enabled once per cluster.
Change-Id: I241e72f21982142ba290c7547df6f434e6a6a98d
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| #
a2847172 |
| 05-Nov-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.
Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
|