feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU

feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.

These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.

For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1

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feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The dif

feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)

Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.

Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.

Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13

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feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arran

feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).

Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.

While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.

Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.

In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b

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feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utili

feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different

This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827

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feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRA

feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRAM1 bank. If we want to access it it needs
to be mapped to memory.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I45e0fbb016e8f615d41b6ad9da0d1e7b466ece72

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Merge "build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag" into integration

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga wi

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga with LTO enabled extra '-nostdlib' has to be
supplied to the linker at least, otherwise build fails with an error
about many undefined references in libc.
Since this option is defined as part of common TF_LDFLAGS already,
just use that variable with couple extra options.

Change-Id: Iaab72d894317c91af5b7d770652e4353b32aae88
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total c

feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.

Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.

Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847

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feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co

feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co-developed-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1f7d7c1c6a5ef67541097ab04670343282458aeb

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refactor(tc): unify all the spmc manifests

The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM info

refactor(tc): unify all the spmc manifests

The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM information separately.

This has some deliberate side effects: the test configuration gets the
full secure memory address space and drops the 0x7000000 region as that
was accidentally copied over from the FVP platform and doesn't apply to
TC.

Also optee unconditionally gets the smaller mem_size as it's been
working fine and simplifies the manifest.

Small touch up is that mem_size-s are now in hex but otherwise the same
number.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iea23f9769235eea32afa374952b9a0e4f6d3e9a1

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feat(arm): add trusty_sp_fw_config build option

Also increase add PLAT_ARM_SP_MAX_SIZE to override the default
ARM_SP_MAX_SIZE to support Trusty image and move OPTEE_SP_FW_CONFIG
documentation to bu

feat(arm): add trusty_sp_fw_config build option

Also increase add PLAT_ARM_SP_MAX_SIZE to override the default
ARM_SP_MAX_SIZE to support Trusty image and move OPTEE_SP_FW_CONFIG
documentation to build-internals.rst as it's not externally set-able.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ief90ae9113d32265ee2200f35f3e517b7b9a4bea

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fix(tc): do not enable MPMM and Aux AMU counters always

There are requirements in which the MPMM and Auxiliary AMU counters have
to be disabled. Hence removing the "override" here which helps in
dis

fix(tc): do not enable MPMM and Aux AMU counters always

There are requirements in which the MPMM and Auxiliary AMU counters have
to be disabled. Hence removing the "override" here which helps in
disabling them during the build.

Change-Id: I2c0a808d5d9968082a508a9206e34f7a57f2e33a
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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fix(spm): reduce verbosity on passing tf-a-tests

Reduce info messages verbosity for RME test cases:

INFO: Sip Call - Protect memory
INFO: Sip Call - Unprotect memory
INFO: Sip Call - Prote

fix(spm): reduce verbosity on passing tf-a-tests

Reduce info messages verbosity for RME test cases:

INFO: Sip Call - Protect memory
INFO: Sip Call - Unprotect memory
INFO: Sip Call - Protect memory
INFO: Sip Call - Unprotect memory

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0bdb545bc6576110dd740ecda8130618f51ed710

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refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd

Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of

refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd

Currently, there are several reference to "SGI" or "sgi" in comments or
as macro prefix within the neoverse_rd directory. As part of the
migration to neoverse_rd, rename all occurences of "SGI/sgi" to
"Neoverse-RD" or the "NRD" prefix accordingly. All references in
comments are rephrased as "Neoverse RD platforms". References in code
are renamed as "NRD"/"nrd" accordingly.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iec195427ff2bee565cb4a325a1a22892be95ae16

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refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"

As of now, several internal macros utilize "CSS_SGI" as their prefix.
Given the change to neoverse_rd, and the subsequent migration out of th

refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"

As of now, several internal macros utilize "CSS_SGI" as their prefix.
Given the change to neoverse_rd, and the subsequent migration out of the
css directory, the prefix "CSS_SGI" is no longer appropriate.
Therefore, update the macro prefixes to "NRD" for consistency and
clarity.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3d1a9dba3e83f6e107379fc5bcf8256cc93d8c3d

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refactor(sgi): move apis and types to "nrd" prefix

Currently, functions and types internal to "neoverse_rd" platforms are
named with "sgi" as the prefix. Since common code and platforms are no
longe

refactor(sgi): move apis and types to "nrd" prefix

Currently, functions and types internal to "neoverse_rd" platforms are
named with "sgi" as the prefix. Since common code and platforms are no
longer under the "sgi" umbrella, move the prefix to "nrd". This change
would amend the prefixes for functions, types and objects.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I706a82bddf55c3be7cf9cef9aaa5df6d420098ca

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refactor(sgi): replace build-option prefix to "NRD"

As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed t

refactor(sgi): replace build-option prefix to "NRD"

As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed to "neoverse_rd" and the source files have been migrated out of
the css directory, replace the prefix "CSS_SGI" with "NRD".

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I27989ff42404d823dd2a8cd22ff485497ccb62d4

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refactor(sgi): move neoverse_rd out of css

Currently, neoverse_rd is hosted under the "css" directory. However,
"css" directory is more relevant for hosting css definitions and
corresponding sources

refactor(sgi): move neoverse_rd out of css

Currently, neoverse_rd is hosted under the "css" directory. However,
"css" directory is more relevant for hosting css definitions and
corresponding sources. Since neoverse_rd hosts source and header for css
and soc, move neoverse_rd from css to board folder. Consolidate common
sources and headers under neoverse_rd/common. Additionally, group RD-V1,
RD-V1-MC, RD-N2, RD-N1-Edgex2 and SGI-575 within neoverse_rd/platform.
With the changes in this commit, the tree view would look as follows:

plat/arm/board/neoverse_rd/
├── common
│   ├── arch
│   ├── include
│   └── ras
└── platform
├── rdn1edge
├── rdn2
├── rdv1
├── rdv1mc
└── sgi575

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iaccc86bc9d415f5c045c834902241fcf3c00277b

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refactor(sgi): move from "sgi" to "neoverse_rd"

Currently, reference design platforms such as RD-N2, RD-N1-Edge,
RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source
directory. The "sg

refactor(sgi): move from "sgi" to "neoverse_rd"

Currently, reference design platforms such as RD-N2, RD-N1-Edge,
RD-V1-MC, RD-V1 and SGI-575 utilize "css/sgi" as the common source
directory. The "sgi" prefix originated from the System Guidance for
Infrastructure (SGI) and was initially associated with the SGI-575
platform. However, subsequent platforms released were under the Neoverse
Reference Design product name.

To align with the Neoverse Reference Design nomenclature, rename the
common source directory from "css/sgi" to "css/neoverse_rd" and update
all file prefixes from "sgi" to "nrd."

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I3dcbb31b9ab202e82caf25218ba33c520dcea4e4

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feat(sgi): remove unused SGI_PLAT build-option

Currently, the common makefile has reference to "SGI_PLAT" build-option.
This however is not set by any of the platforms that makes use of the
common m

feat(sgi): remove unused SGI_PLAT build-option

Currently, the common makefile has reference to "SGI_PLAT" build-option.
This however is not set by any of the platforms that makes use of the
common makefile. Therefore, remove the unused SGI_PLAT build-option.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I6cc0b8d87222c7b3aef998774cee964a920cceb6

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fix(sgi): align to misra rule for braces

Misra rule states that braces have to be used with every 'if', 'else',
'for', 'do', and 'while' statement. In order to align with the said
rule, add braces f

fix(sgi): align to misra rule for braces

Misra rule states that braces have to be used with every 'if', 'else',
'for', 'do', and 'while' statement. In order to align with the said
rule, add braces for the statements within plat_css_get_scmi_info.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I826685e92926d90734b11d870dd624b11c9d1c30

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feat(rde1edge): remove support for RD-E1-Edge

As RD-E1_Edge is no longer actively supported and has been in the
deprecated list for a while, remove its support.

Signed-off-by: Rohit Mathew <Rohit.M

feat(rde1edge): remove support for RD-E1-Edge

As RD-E1_Edge is no longer actively supported and has been in the
deprecated list for a while, remove its support.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iff66ad498dd99e44e2e6b79251ba2cbefbd5f3eb

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fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled

As of now, TOS_FW_CONFIG (trusted OS config) gets populated by default
for RD-N2. However, TOS_FW_CONFIG is required only when SPMC_AT

fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled

As of now, TOS_FW_CONFIG (trusted OS config) gets populated by default
for RD-N2. However, TOS_FW_CONFIG is required only when SPMC_AT_EL3 is
enabled. As the platform should support SPMC_AT_EL3 disabled mode as
well, populate TOS_CONFIG only when SPMC_AT_EL3 is enabled.
Additionally, building of rdn2_stmm_sel0_manifest.dtb is made
conditional to align with this configuration.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I9077d44b21d32ba7bf6b3b1c539662c14785ca6b

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fix(board): update spi_id max for sgi multichip platforms

According to GIC-600 TRM, 960 SPIs could be supported on a platform.
However, with the current configuration, platforms such as RD-V1-MC and

fix(board): update spi_id max for sgi multichip platforms

According to GIC-600 TRM, 960 SPIs could be supported on a platform.
However, with the current configuration, platforms such as RD-V1-MC and
RD-N1-Edge Dual-Chip utilize a much smaller range. With commit
'a02a45dfe' gic600 driver is updated to get the max SPI id from the
GIC-600 and probe for the corresponding GIC instance for each SPI id.
Since RD-V1-MC and RD-N1-Edge Dual-Chip supports wider range, increase
SPI range for the chip 0 to max SPI range supported.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia8c02c6d999033af33d8e7a0bedc7b73c6552ab4

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build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag

This change includes adding new CORSTONE1000_WITH_BL32 preprocessor
flag on the basis of NEED_BL32 flag. This flag allows us to run

build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag

This change includes adding new CORSTONE1000_WITH_BL32 preprocessor
flag on the basis of NEED_BL32 flag. This flag allows us to run the
TF-A with or without loading BL32 image. This feature is required to
add the support of Corstone-1000 FVP in TF-A open CI.
After this, we can run the TF-A tftf tests with or without
executing BL32 image, which is optee in case of Corstone-1000.

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Change-Id: Idacbd3883473473841481a2032314db8c9715b1f

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