Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

show more ...

refactor(arm): switch to rse_mbx_init

The rse_comms_init() function will be removed. The new function to use
is rse_mbx_init() for the MHU mailbox initialization.

Change-Id: I1932500ef71b6e895f0ee1

refactor(arm): switch to rse_mbx_init

The rse_comms_init() function will be removed. The new function to use
is rse_mbx_init() for the MHU mailbox initialization.

Change-Id: I1932500ef71b6e895f0ee164ee9c2b58becf4409
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Ch

refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I12f3b8a38a5369decb4b97f8aceeb0dc81cbea28

show more ...

refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, M

refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, MHUv1, MHUv2, MHUv3...

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia72e590088ce62ba8c9009f341b6135926947bee

show more ...

fix(arm): don't race on the build directory

Wait for it to have been created. This is the same issue as
commit db69d118294f08aae86378c98aa082ac73e15b73.

Change-Id: I32bd0c713e2837563d32131fb0beddb5

fix(arm): don't race on the build directory

Wait for it to have been created. This is the same issue as
commit db69d118294f08aae86378c98aa082ac73e15b73.

Change-Id: I32bd0c713e2837563d32131fb0beddb5533c0792
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`
chore(psci): drop skip_wfi variable
feat(arm): convert arm platforms to expect a wakeup
fix(cpus): avoid SME related loss of context on powerdown
feat(psci): allow cores to wake up from powerdown
refactor: panic after calling psci_power_down_wfi()
refactor(cpus): undo errata mitigations
feat(cpus): add sysreg_bit_toggle

show more ...

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB of PCIe memory region 1 and 3GB of
PCIe memory region 2 to FVP PAS regions array.

Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

show more ...

feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is c

feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is controlled
by 'RME_GPT_BITLOCK_BLOCK' build option and 'PLAT_ARM_PPS'
macro defined in platform_def.h which specifies the size
of protected physical address space in bytes.
'PLAT_ARM_PPS' takes values from 4GB to 4PB supported by
Arm architecture.

Change-Id: Icf620b5039e45df6828d58fca089cad83b0bc669
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

show more ...

chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc0813

chore(gpt): define PPS in platform header files

Define protected physical address size in bytes
PLAT_ARM_PPS macro for FVP and RDV3 in platform_def.h
files.

Change-Id: I7f6529dfbb8df864091fbefc08131a0e6d689eb6
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

show more ...

feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unu

feat(fvp): allocate L0 GPT at the top of SRAM

This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.

Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

show more ...

feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Upda

feat(rmm): add PCIe IO info to Boot manifest

- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.

Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

show more ...

feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library a

feat(fvp): define single Root region

For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library and use GPT
mapping with Contiguous descriptor of
larger block size.

Change-Id: I70f6babaebc14e5e0bce033783ec423c8a26c542
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

show more ...

feat(cpus): add ENABLE_ERRATA_ALL flag

Now that all errata flags are all conveniently in a single list we can
make sweeping decisions about their values. The first use-case is to
enable all errata i

feat(cpus): add ENABLE_ERRATA_ALL flag

Now that all errata flags are all conveniently in a single list we can
make sweeping decisions about their values. The first use-case is to
enable all errata in TF-A. This is useful for CI runs where it is
impractical to list every single one. This should help with the long
standing issue of errata not being built or tested.

Also add missing CPUs with errata to `ENABLE_ERRATA_ALL` to enable all
errata builds in CI.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2b456d304d7bf3215c7c4f4fd70b56ecbcb09979

show more ...

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3): define SPMC manifest base address
feat(arm): add a macro for SPMC manifest base address
feat(rdv3): add carveout for BL32 image
feat(rdv3): introduce platform handler for Group0 interrupt
feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled
fix(neoverse-rd): set correct SVE vector lengths

show more ...

fix(psci): check if a core is the last one in a requested power level

PSCI OS initiated is usually implemented with the extended state id
format, however this does not have to be the case. When this

fix(psci): check if a core is the last one in a requested power level

PSCI OS initiated is usually implemented with the extended state id
format, however this does not have to be the case. When this is the
case, the original format will carry the requested power level in
the PowerLevel field. To validate that the requested power state is
valid we must save it so that later when we call
psci_is_last_cpu_to_idle_at_pwrlvl() it checks the right level (instead
of a default 0).

This came up when testing 01959a1656a08dacd1d036d0441165d52bf7563e for
all configurations.

Change-Id: Iaab88c1910467282ae524861446283acddd9d977
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(rdv3): enable the support to fetch dynamic config

To enable the support to load Hafnium as BL32, BL31 needs firmware
configuration info to get BL32 manifest load location. The load address
of B

feat(rdv3): enable the support to fetch dynamic config

To enable the support to load Hafnium as BL32, BL31 needs firmware
configuration info to get BL32 manifest load location. The load address
of BL32 is passed via firmware config info.

Add the support to get the address using fconf framework from dynamic
config info.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I3a2a5706789ed290dc7f4a67e62e03751b930c02

show more ...

feat(rdv3): add dts files to enable hafnium as BL32

On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32

feat(rdv3): add dts files to enable hafnium as BL32

On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32 image. SP is loaded by SP load framework and configured by
Hafnium.

Add the dts files needed to enable load and configuration of hafnium and
SP.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd

show more ...

feat(rdv3): define SPMC manifest base address

ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest
used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to
the top of T

feat(rdv3): define SPMC manifest base address

ARM_SPMC_MANIFEST_BASE defines the base address of the SPMC manifest
used by BL32. In the non-RESET_TO_BL31 case, it is defined relative to
the top of Trusted SRAM. However, for RESET_TO_BL31, the
PLAT_ARM_SPMC_MANIFEST_BASE macro can be used to set it to a different
location which is then used to populate ARM_SPMC_MANIFEST_BASE.

As the RD-V3 platform and its variants have a different SRAM layout
compared to that defined in arm_def.h, define the
PLAT_ARM_SPMC_MANIFEST_BASE macro to an address suitable for this
platform and its variants.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I36e1eb21ab3d1c68bddb52c62198fcdfc40d8993

show more ...

feat(arm): add a macro for SPMC manifest base address

In RESET_TO_BL31, the SPMC manifest base address that is utilized by
bl32_image_ep_info has to be statically defined as DT is not available.
Com

feat(arm): add a macro for SPMC manifest base address

In RESET_TO_BL31, the SPMC manifest base address that is utilized by
bl32_image_ep_info has to be statically defined as DT is not available.
Common arm code sets this to the top of SRAM using macros but it can be
different for some platforms. Hence, introduce the macro
PLAT_ARM_SPMC_MANIFEST_BASE that could be re-defined by platform as per
their use-case. Platforms that utilize arm_def.h would use the existing
value from arm common code.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I4491749ad2b5794e06c9bd11ff61e2e64f21a948

show more ...

Merge "fix(arm): create build directory before key generation" into integration

fix(rdn2): correct RD-N2 StMM uuid format

Edk2 converts StMM GUID to UUID format, which is used in FF-A and linux
kernel. StMM manifest currently provides GUID format. Correcting this to
UUID format

fix(rdn2): correct RD-N2 StMM uuid format

Edk2 converts StMM GUID to UUID format, which is used in FF-A and linux
kernel. StMM manifest currently provides GUID format. Correcting this to
UUID format.

Change-Id: Ie94728e5ea74d3d9935e0af9a2a601cbafe5ad3d
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

show more ...

Merge changes from topic "us_tc_trng" into integration

* changes:
feat(tc): get entropy with PSA Crypto API
feat(psa): add interface with RSE for retrieving entropy
fix(psa): guard Crypto APIs

Merge changes from topic "us_tc_trng" into integration

* changes:
feat(tc): get entropy with PSA Crypto API
feat(psa): add interface with RSE for retrieving entropy
fix(psa): guard Crypto APIs with CRYPTO_SUPPORT
feat(tc): enable trng
feat(tc): initialize the RSE communication in earlier phase

show more ...

feat(rdv3): add carveout for BL32 image

Add and map the carveout for loading Hafnium as BL32 image. Also define
PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions.

Signed-off-by: Rohit Mathew <rohi

feat(rdv3): add carveout for BL32 image

Add and map the carveout for loading Hafnium as BL32 image. Also define
PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I2845eb6807a127c9f6b92de2dabc9a58d25bd4d4

show more ...

feat(rdv3): introduce platform handler for Group0 interrupt

This patch introduces a handler for RD-V3 variants to handle Group0
secure interrupts. Currently, it is empty but serves as a placeholder

feat(rdv3): introduce platform handler for Group0 interrupt

This patch introduces a handler for RD-V3 variants to handle Group0
secure interrupts. Currently, it is empty but serves as a placeholder
for future Group0 interrupt sources.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: Ifa418094f6075a6cdc33e63eec1825103bbf6d68

show more ...

feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled

Larger stack size is needed when S-EL2 SPMC is enabled. This is required
because BL31 xlat map framework makes more nested calls w

feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled

Larger stack size is needed when S-EL2 SPMC is enabled. This is required
because BL31 xlat map framework makes more nested calls when this
feature is enabled.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: Ib3f2abf38b576ba96402dab4ba995d8b648b4cc7

show more ...