History log of /rk3399_ARM-atf/plat/arm/ (Results 2251 – 2275 of 2547)
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d08f8c6a20-Sep-2017 Sandrine Bailleux <sandrine.bailleux@arm.com>

FVP: Include utils_def.h instead of utils.h

platform_def.h doesn't need all the definitions in utils.h,
the ones in utils_def.h are enough. This patch is related
to the changes introduced by commit

FVP: Include utils_def.h instead of utils.h

platform_def.h doesn't need all the definitions in utils.h,
the ones in utils_def.h are enough. This patch is related
to the changes introduced by commit 53d9c9c85b.

Change-Id: I4b2ff237a2d7fe07a7230e0e49b44b3fc2ca8abe
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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f18f5f9813-Sep-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1092 from jeenu-arm/errata-workarounds

Errata workarounds

487c869d12-Sep-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1088 from soby-mathew/sm/sds_scmi

Introduce SDS Driver

ff07ca2011-Sep-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1086 from robertovargas-arm/dead_loop

juno: Fix bug in plat_get_my_entrypoint

96ff260104-Aug-2017 Eleanor Bonnici <Eleanor.bonnici@arm.com>

Juno: Disable 859971 and 859972 errata workarounds

Earlier patches added errata workarounds 859972 for Cortex-A72, and
859972 for Cortex-A57 CPUs. Explicitly disable the workaround for Juno.

Also r

Juno: Disable 859971 and 859972 errata workarounds

Earlier patches added errata workarounds 859972 for Cortex-A72, and
859972 for Cortex-A57 CPUs. Explicitly disable the workaround for Juno.

Also reorganize errata workaround flags.

No functional changes.

Change-Id: I3fe3745de57d77e5bf52012826d3969fe5d4844e
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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5457874507-Sep-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1080 from soby-mathew/eb/RSA-PKCS1-5_support_1

Support legacy RSA PKCS#1 v1.5 in cert create

18e279eb12-Jun-2017 Soby Mathew <soby.mathew@arm.com>

CSS: Changes for SDS framework

This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI b

CSS: Changes for SDS framework

This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI build flag is now renamed to
`CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on
CSS platforms. Also some of the workarounds applied for SCMI are
now removed with SDS in place.

Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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9bedda4a12-Jun-2017 Soby Mathew <soby.mathew@arm.com>

SDS: Introduce the sds drivers

This patch introduces the driver for Shared-Data-Structure (SDS)
framework which will be used for communication between SCP and AP
CPU. The SDS framework is intended t

SDS: Introduce the sds drivers

This patch introduces the driver for Shared-Data-Structure (SDS)
framework which will be used for communication between SCP and AP
CPU. The SDS framework is intended to replace the Boot-Over-MHU
(BOM) protocol used currently for the communication

Change-Id: Ic174291121f4e581b174cce3389d22d6435f7269
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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0a04c69a12-Jun-2017 Soby Mathew <soby.mathew@arm.com>

Split CSS makefile for sp_min on Juno

This patch factors out common files required for sp_min for all CSS
platforms from the JUNO specific makefile to a the new `css_sp_min.mk`
makefile. This also a

Split CSS makefile for sp_min on Juno

This patch factors out common files required for sp_min for all CSS
platforms from the JUNO specific makefile to a the new `css_sp_min.mk`
makefile. This also allows the common build options that affect CSS
platforms to be configured in a central makefile for sp_min.

Change-Id: Ida952d8833b1aa5eda77ae0a6664a4632aeab24c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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d9b7636e01-Sep-2017 Roberto Vargas <roberto.vargas@arm.com>

juno: Fix bug in plat_get_my_entrypoint

plat_get_my_entrypoint was branching to juno_do_reset_to_aarch_32_state,
which is not supposed to return, and in case of returning it implemented
an infinite

juno: Fix bug in plat_get_my_entrypoint

plat_get_my_entrypoint was branching to juno_do_reset_to_aarch_32_state,
which is not supposed to return, and in case of returning it implemented
an infinite loop. The problem was that plat_get_my_entrypoint was using
"b" instead of "bl", so juno_do_reset_to_aarch_32_state was returning to
the caller of plat_get_my_entrypoint instead of stop the system with a
panic.

To avoid this problem juno_do_reset_to_aarch_32_state was modified to
call directly to plat_panic_handler if it tries to return.

Change-Id: I591cf2dd78d27d8568fb15b91366e4b3dce027b5
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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b3ba6fda01-Sep-2017 Soby Mathew <soby.mathew@arm.com>

Fix BL2 memory map when OP-TEE is the Secure Payload

The commit 3eb2d67 optimizes the memory map for BL2 when TSP
is not present. But this also broke OP-TEE as it was reusing
the TSP mapping. This p

Fix BL2 memory map when OP-TEE is the Secure Payload

The commit 3eb2d67 optimizes the memory map for BL2 when TSP
is not present. But this also broke OP-TEE as it was reusing
the TSP mapping. This patch fixes this problem by adding a
separate mapping for OP-TEE in the BL2 memory map table.

Change-Id: I130a2ea552b7b62d8478081feb1f4ddf5292a118
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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085bac2b31-Aug-2017 danh-arm <dan.handley@arm.com>

Merge pull request #1072 from sandrine-bailleux-arm/sb/tsp-mapping

ARM platforms: Map TSP only when TSPD is included

2091755c31-Aug-2017 Soby Mathew <soby.mathew@arm.com>

Export KEY_ALG as a user build option

The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undoc

Export KEY_ALG as a user build option

The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undocumented and did not have a global default
value. This patch corrects this and also adds changes to derive the
value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the
platform. The corresponding assignment of these variables are also now
removed from the `arm_common.mk` makefile.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4

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3eb2d67230-Aug-2017 Sandrine Bailleux <sandrine.bailleux@arm.com>

ARM platforms: Map TSP only when TSPD is included

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry

ARM platforms: Map TSP only when TSPD is included

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry in the plat_arm_mmap[] array and avoids to map extra memory when
it's not needed.

Change-Id: I6ae60822ff8f0de198145925b0b0d45355179a94
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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bea363ad22-Aug-2017 Soby Mathew <soby.mathew@arm.com>

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`ass

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`assert()` will not generate the strings implied in the expression taken
as parameter. This allows to save some memory when Juno is built for
LOG_LEVEL = LOG_LEVEL_VERBOSE and DEBUG = 1.

Fixes ARM-software/tf-issues#511

Change-Id: Id84a40f803ab07a5a8f6e587167af96694a07d04
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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a1f5a9e530-Aug-2017 Roberto Vargas <roberto.vargas@arm.com>

Don't use zero_normalmem in bl2_platform_setup

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of E

Don't use zero_normalmem in bl2_platform_setup

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of EL3_PAYLOAD_BASE bl2_platform_setup was
calling zero_normalmem with device memory and it generated an abort.

Change-Id: If013603f209a12af488a9c54481f97a8f395b26a
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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77544efb29-Aug-2017 danh-arm <dan.handley@arm.com>

Merge pull request #1071 from jeenu-arm/syntax-fix

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

1958316923-Aug-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

The current definition of ARM_INSTANTIATE_LOCK macro includes a
semicolon, which means it's omitted where it's used. This is anomalous
for a C state

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

The current definition of ARM_INSTANTIATE_LOCK macro includes a
semicolon, which means it's omitted where it's used. This is anomalous
for a C statement in global scope.

Fix this by removing semicolon from the definition; and where it's a
NOP, declare a file-scoped variable explicitly tagged as unused to avoid
compiler warning.

No functional changes.

Change-Id: I2c1d92ece4777e272a025011e03b8003f3543335
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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48f4bcd229-Aug-2017 danh-arm <dan.handley@arm.com>

Merge pull request #1068 from jenswi-linaro/optee_arm_plat

Optee arm platform common

afb3343225-Aug-2017 davidcunado-arm <david.cunado@arm.com>

Merge pull request #1064 from islmit01/im/shifted_afinity

FVP: Always assume shifted affinity with MT bit

810d921325-Aug-2017 Jens Wiklander <jens.wiklander@linaro.org>

FVP: bl2: optionally map ARM_OPTEE_PAGEABLE_LOAD_MEM

If SPD_opteed is defined map ARM_OPTEE_PAGEABLE_LOAD_MEM in bl2 to
allow loading of OP-TEE paged part.

Signed-off-by: Jens Wiklander <jens.wikla

FVP: bl2: optionally map ARM_OPTEE_PAGEABLE_LOAD_MEM

If SPD_opteed is defined map ARM_OPTEE_PAGEABLE_LOAD_MEM in bl2 to
allow loading of OP-TEE paged part.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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8431635b17-Aug-2017 Isla Mitchell <isla.mitchell@arm.com>

FVP: Always assume shifted affinity with MT bit

At present, the MPIDR validation on FVP relies on MT bit set along
with shifted affinities. This currently is additionally dependent
on the FVP model

FVP: Always assume shifted affinity with MT bit

At present, the MPIDR validation on FVP relies on MT bit set along
with shifted affinities. This currently is additionally dependent
on the FVP model being of variant C. This however should be based
on the presence of MT bit alone.

This patch makes the change to always assume that the affinities
are shifted in the FVP model when MT bit is present.

Change-Id: I09fcb0126e1b38d29124bdeaf3450a60b95d485d
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

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3bbe34e528-Jul-2017 Roberto Vargas <roberto.vargas@arm.com>

norflash: Add full status check

The nor_XXXXX functions may fail due to different reasons, and it
is convenient to do a full check to detect any failure. It is also
a good idea to have a specific fu

norflash: Add full status check

The nor_XXXXX functions may fail due to different reasons, and it
is convenient to do a full check to detect any failure. It is also
a good idea to have a specific function to do a full status check,
because new checks can be added to this function and they will be
incorporated automatically to any function calling it.

Change-Id: I54fed913e37ef574c1608e94139a519426348d12
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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784502ae28-Jul-2017 Roberto Vargas <roberto.vargas@arm.com>

norflash: Add nor_erase() to NOR driver

NOR memory only supports setting bits to 1. To clear a bit, set to zero,
the NOR memory needs to be erased.

Change-Id: Ia82eb15a5af9a6d4fc7e5ea2b58e6db87226b

norflash: Add nor_erase() to NOR driver

NOR memory only supports setting bits to 1. To clear a bit, set to zero,
the NOR memory needs to be erased.

Change-Id: Ia82eb15a5af9a6d4fc7e5ea2b58e6db87226b351
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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b4b09ca526-Jul-2017 Roberto Vargas <roberto.vargas@arm.com>

norflash: Clear status register before sending commands

The status register bits remain until explicitly cleared, which means
that a command can be incorrectly considered to have generated an error

norflash: Clear status register before sending commands

The status register bits remain until explicitly cleared, which means
that a command can be incorrectly considered to have generated an error -
for example, after reset the status register contents may be unknown or
if a previous command had failed.

This patch clears the status register before beginning any command to
be sure that the status register only represents information about the
current operation.

Change-Id: I9e98110ee24179937215461c00b6543a3467b350
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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