| e8ad3975 | 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(brbe): add BRBE support for NS world" into integration |
| 78c82cd0 | 06-May-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "ja/boot_protocol" into integration
* changes:
fix(sptool): update Optee FF-A manifest
feat(sptool): delete c version of the sptool
feat(sptool): use python version of
Merge changes from topic "ja/boot_protocol" into integration
* changes:
fix(sptool): update Optee FF-A manifest
feat(sptool): delete c version of the sptool
feat(sptool): use python version of sptool
feat(sptool): python version of the sptool
refactor(sptool): use SpSetupActions in sp_mk_generator.py
feat(sptool): add python SpSetupActions framework
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| be96158f | 06-May-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(fvp): fix NULL pointer dereference issue" into integration |
| 744ad974 | 28-Jan-2022 |
johpow01 <john.powell@arm.com> |
feat(brbe): add BRBE support for NS world
This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disab
feat(brbe): add BRBE support for NS world
This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disabled for all secure world, and cannot be used with ENABLE_RME.
This option is disabled by default, however, the FVP platform makefile
enables it for FVP builds.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I576a49d446a8a73286ea6417c16bd0b8de71fca0
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| a42b426b | 04-May-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
fix(fvp): fix NULL pointer dereference issue
Fixed below NULL pointer dereference issue reported by coverity scan
by asserting the hw_config_info is not NULL.
*** CID 378361: Null pointer derefere
fix(fvp): fix NULL pointer dereference issue
Fixed below NULL pointer dereference issue reported by coverity scan
by asserting the hw_config_info is not NULL.
*** CID 378361: Null pointer dereferences (NULL_RETURNS)
/plat/arm/board/fvp/fvp_bl2_setup.c: 84 in plat_get_next_bl_params()
78
79 /* To retrieve actual size of the HW_CONFIG */
80 param_node = get_bl_mem_params_node(HW_CONFIG_ID);
81 assert(param_node != NULL);
82
83 /* Copy HW config from Secure address to NS address */
>>> CID 378361: Null pointer dereferences (NULL_RETURNS)
>>> Dereferencing "hw_config_info", which is known to be "NULL".
84 memcpy((void *)hw_config_info->ns_config_addr,
85 (void *)hw_config_info->config_addr,
86 (size_t)param_node->image_info.image_size);
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: Iaf584044cfc3b2583862bcc1be825966eaffd38e
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| 44639ab7 | 29-Nov-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
feat(plat/fvp): add EL3 SPMC #defines
Introduce additional #defines for running with the EL3
SPMC on the FVP.
The increase in xlat tables has been chosen to allow
the test cases to complete success
feat(plat/fvp): add EL3 SPMC #defines
Introduce additional #defines for running with the EL3
SPMC on the FVP.
The increase in xlat tables has been chosen to allow
the test cases to complete successfully and may need
adjusting depending on the desired usecase.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I7f44344ff8b74ae8907d53ebb652ff8def2d2562
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| a34ccd4c | 19-Aug-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
test(plat/fvp/lsp): add example logical partition
Add an example logical partition to the FVP platform that
simply prints and echos the contents of a direct request
with the appropriate direct respo
test(plat/fvp/lsp): add example logical partition
Add an example logical partition to the FVP platform that
simply prints and echos the contents of a direct request
with the appropriate direct response.
Change-Id: Ib2052c9a63a74830e5e83bd8c128c5f9b0d94658
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
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| d6fbcc57 | 05-May-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mp/delete_platforms" into integration
* changes:
refactor(mt6795): remove mediatek's mt6795 platform
refactor(sgm775): remove Arm sgm775 platform |
| ca0fdbd8 | 08-Apr-2022 |
J-Alves <joao.alves@arm.com> |
fix(sptool): update Optee FF-A manifest
Change the OPTEE FF-A manifest to comply with changes to the sp pkg [1].
The sptool packs the image at the default offset of 0x4000, if it is not
provided in
fix(sptool): update Optee FF-A manifest
Change the OPTEE FF-A manifest to comply with changes to the sp pkg [1].
The sptool packs the image at the default offset of 0x4000, if it is not
provided in the arguments.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14507
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I647950410114f7fc24926696212bb7f8101390ac
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| 15e54148 | 04-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
refactor(sgm775): remove Arm sgm775 platform
Arm's sgm775 platform was deprecated in 2.5 release and as per [1] a
platform which has been marked deprecated should be removed from repo
after 2 releas
refactor(sgm775): remove Arm sgm775 platform
Arm's sgm775 platform was deprecated in 2.5 release and as per [1] a
platform which has been marked deprecated should be removed from repo
after 2 release cycle.
[1] https://trustedfirmware-a.readthedocs.io/en/latest/plat/deprecated.html?highlight=deprecated
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I3cce6f330a1def725188eefd558bd0e4ec559725
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| 1ced6cad | 03-May-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "refactor-hw-config-load" into integration
* changes:
docs(fvp): update loading addresses of HW_CONFIG
docs(fconf): update device tree binding for FCONF
feat(fvp): upd
Merge changes from topic "refactor-hw-config-load" into integration
* changes:
docs(fvp): update loading addresses of HW_CONFIG
docs(fconf): update device tree binding for FCONF
feat(fvp): update HW_CONFIG DT loading mechanism
refactor(st): update set_config_info function call
refactor(fvp_r): update set_config_info function call
refactor(arm): update set_config_info function call
feat(fconf): add NS load address in configuration DTB nodes
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| 06796a08 | 28-Apr-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(smmu): configure SMMU Root interface" into integration |
| 52a314af | 04-Feb-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
feat(smmu): configure SMMU Root interface
This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions
feat(smmu): configure SMMU Root interface
This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions originated from a non-secure or secure device upstream
to an SMMU. It re-uses the boot time GPT base address and configuration
programmed on the PE.
The root register file offset is platform dependent and has to be
supplied on a model command line.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07
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| 861250c3 | 19-Apr-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(arm): fix fvp and juno build with USE_ROMLIB option
Change-Id: I8a9b30a952be594435003f0d684e3faad484e8b8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
| 39f0b86a | 15-Mar-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): update HW_CONFIG DT loading mechanism
Currently, HW-config is loaded into non-secure memory, which mean
a malicious NS-agent could tamper with it. Ideally, this shouldn't
be an issue sinc
feat(fvp): update HW_CONFIG DT loading mechanism
Currently, HW-config is loaded into non-secure memory, which mean
a malicious NS-agent could tamper with it. Ideally, this shouldn't
be an issue since no software runs in non-secure world at this time
(non-secure world has not been started yet).
It does not provide a guarantee though since malicious external
NS-agents can take control of this memory region for update/corruption
after BL2 loads it and before BL31/BL32/SP_MIN consumes it. The threat
is mapped to Threat ID#3 (Bypass authentication scenario) in threat
model [1].
Hence modified the code as below -
1. BL2 loads the HW_CONFIG into secure memory
2. BL2 makes a copy of the HW_CONFIG in the non-secure memory at an
address provided by the newly added property(ns-load-address) in
the 'hw-config' node of the FW_CONFIG
3. SP_MIN receives the FW_CONFIG address from BL2 via arg1 so that
it can retrieve details (address and size) of HW_CONFIG from
FW_CONFIG
4. A secure and non-secure HW_CONFIG address will eventually be used
by BL31/SP_MIN/BL32 and BL33 components respectively
5. BL31/SP_MIN dynamically maps the Secure HW_CONFIG region and reads
information from it to local variables (structures) and then
unmaps it
6. Reduce HW_CONFIG maximum size from 16MB to 1MB; it appears
sufficient, and it will also create a free space for any future
components to be added to memory
[1]: https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/threat_model.html
Change-Id: I1d431f3e640ded60616604b1c33aa638b9a1e55e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 8b95e848 | 31-Jan-2022 |
Zelalem Aweke <zelalem.aweke@arm.com> |
refactor(context mgmt): add cm_prepare_el3_exit_ns function
As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' fun
refactor(context mgmt): add cm_prepare_el3_exit_ns function
As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' function. The function is
a wrapper to 'cm_prepare_el3_exit' function for Non-secure state.
When EL2 sysregs context exists (CTX_INCLUDE_EL2_REGS is
enabled) EL1 and EL2 sysreg values are restored from the context
instead of directly updating the registers.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9b071030576bb05500d54090e2a03b3f125d1653
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|
| 2d1ba79c | 12-Apr-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "style(plat/arm/corstone1000): resolve checkpatch warnings" into integration |
| def5571d | 21-Feb-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
refactor(arm): use MBEDTLS_CONFIG_FILE macro
Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3a
refactor(arm): use MBEDTLS_CONFIG_FILE macro
Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3ab1e69481b2c37a6f7455a106b6e
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| 510dc79c | 18-Mar-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
refactor(corstone700): namespace MHU driver filenames
There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.
In preparation for this, rename the Corstone-700 MH
refactor(corstone700): namespace MHU driver filenames
There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.
In preparation for this, rename the Corstone-700 MHU driver source
files and prefix them with the name of the platform to avoid any
ambiguity or name clashes with the upcoming generic MHU driver. Also
rename the header guard accordingly.
This renaming is inline with other platform-specific MHU drivers, such
as the ones used on Broadcom [1], Socionext [2] or Amlogic [3] platforms.
[1] plat/brcm/common/brcm_mhu.h
[2] plat/socionext/synquacer/drivers/mhu/sq_mhu.h
[3] plat/amlogic/common/aml_mhu.c
Change-Id: I8a5e5b16e7c19bf931a90422dfca8f6a2a0663b4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 83b3ed26 | 03-Mar-2022 |
David Vincze <david.vincze@arm.com> |
style(plat/arm/corstone1000): resolve checkpatch warnings
Change-Id: Ic8cb9b0834806675c792018e809d7ba77fbe856f
Signed-off-by: David Vincze <david.vincze@arm.com> |
| ad88c370 | 28-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "rme-attest" into integration
* changes:
feat(rme): add dummy realm attestation key to RMMD
feat(rme): add dummy platform token to RMMD |
| a0435105 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
paramete
feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
parameters:
* Fid (0xC400001B2).
* Attestation key buffer PA (the realm attestation key is copied
at this address by the monitor).
* Attestation key buffer length as input and size of realm
attesation key as output.
* Type of elliptic curve.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I12d8d98fd221f4638ef225c9383374ddf6e65eac
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| 0f9159b7 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC4000
feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC40001B3).
* Platform token PA (the platform token is copied at this address by
the monitor). The challenge object needs to be passed by
the caller in this buffer.
* Platform token len.
* Challenge object len.
When calling the SMC, the platform token buffer received by EL3 contains
the challenge object. It is not used on the FVP and is only printed to
the log.
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I8b2f1d54426c04e76d7a3baa6b0fbc40b0116348
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| c5edb59d | 22-Mar-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(plat/arm): fix SP count limit without dual root CoT" into integration |
| fdb9166b | 16-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(fvp): disable reclaiming init code by default
In anticipation of Spectre BHB workaround mitigation patches, we
disable the RECLAIM_INIT_CODE for FVP platform. Since the spectre
BHB mitigation wo
fix(fvp): disable reclaiming init code by default
In anticipation of Spectre BHB workaround mitigation patches, we
disable the RECLAIM_INIT_CODE for FVP platform. Since the spectre
BHB mitigation workarounds inevitably increase the size of the various
segments due to additional instructions and/or macros, these segments
cannot be fit in the existing memory layout designated for BL31 image.
The issue is specifically seen in complex build configs for FVP
platform. One such config has TBB with Dual CoT and test secure
payload dispatcher(TSPD) enabled. Even a small increase in individual
segment size in order of few bytes might lead to build fails due to
alignment requirements(PAGE_ALIGN to 4KB).
This is needed to workaround the following build failures observed
across multiple build configs:
aarch64-none-elf-ld.bfd: BL31 init has exceeded progbits limit.
aarch64-none-elf-ld.bfd: /work/workspace/workspace/tf-worker_ws_2/trusted_firmware/build/fvp/debug/bl31/bl31.elf section coherent_ram will not fit in region RAM
aarch64-none-elf-ld.bfd: BL31 image has exceeded its limit.
aarch64-none-elf-ld.bfd: region RAM overflowed by 4096 bytes
Change-Id: Idfab539e9a40f4346ee11eea1e618c97e93e19a1
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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