chore: fix preprocessor checks

We can also drop the preprocessor check from plat_gic_init - it was
introduced because the tsp needed to call this function on gicv2 but not
gicv3 and this was the cle

chore: fix preprocessor checks

We can also drop the preprocessor check from plat_gic_init - it was
introduced because the tsp needed to call this function on gicv2 but not
gicv3 and this was the cleanest way to filter this out. Now that we have
the generic driver, the caller has all the tools to cater for this.
Callers have been converted so this is redundant.

Also, the FVP observes different behaviour on debug and release builds
in regards to the contents of plat_params_from_bl2. Make this explicit
so that release builds with ENABLE_ASSERTIONS=1 are possible.

Change-Id: I86959e67460d0c25c558f33c08e6233a8b6eeb7f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(arm): resolve misra rule R11.6 violation" into integration

fix(arm): resolve misra rule R11.6 violation

Fixed below MISRA violation:
- MISRA violation: MC3R1.R11.6:
- A cast shall not be performed between a pointer to void and an
arithmetic data type.

fix(arm): resolve misra rule R11.6 violation

Fixed below MISRA violation:
- MISRA violation: MC3R1.R11.6:
- A cast shall not be performed between a pointer to void and an
arithmetic data type. (i.e cast from integer to void*)
- Fix:
- cast via portable and misra compliant type "uintptr_t" and
use 0U instead of NULL for comparisons.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie3a7561d9a254027c5364485a1d72fc1320dfcad

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Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2

Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2
feat(arm): add support for Transfer List creation

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refactor(arm): simplify early platform setup function in BL31

Refactor `arm_bl31_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in

refactor(arm): simplify early platform setup function in BL31

Refactor `arm_bl31_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
common code. This simplifies the interface for early platform setup.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iff20300d2372e1a9825827ddccbd1b3bc6751e40

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Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add li

Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add lib to sp-min sources
feat(handoff): add 32-bit variant of SRAM layout
feat(handoff): add 32-bit variant of ep info
fix(aarch32): avoid using r12 to store boot params
fix(arm): reinit secure and non-secure tls
refactor(handoff): downgrade error messages

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fix(arm): reinit secure and non-secure tls

Initializing the transfer list using `transfer_list_ensure` allows reuse
of an already initialized transfer list. While this is beneficial when
receiving a

fix(arm): reinit secure and non-secure tls

Initializing the transfer list using `transfer_list_ensure` allows reuse
of an already initialized transfer list. While this is beneficial when
receiving a transfer list and ensuring one exists, it causes issues
during a system RESET if the old content of SRAM is not cleared.

To prevent this, at least one step in the reset path must zero intialise
the transfer list memory. Unless a previous stage explicitly provides a
transfer list via boot arguments, a fresh transfer list should be
created.

This change ensures that BL1 and BL31 properly reinitialize the transfer
lists, preserving correctness for secure and non-secure handoffs in
TF-A.

Change-Id: I3bfaa9e76df932a637031d645e4a22d857a094a5
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

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feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is c

feat(gpt): statically allocate bitlocks array

Statically allocate 'gpt_bitlock' array of fine-grained
'bitlock_t' data structures in arm_bl31_setup.c.
The amount of memory needed for this array is controlled
by 'RME_GPT_BITLOCK_BLOCK' build option and 'PLAT_ARM_PPS'
macro defined in platform_def.h which specifies the size
of protected physical address space in bytes.
'PLAT_ARM_PPS' takes values from 4GB to 4PB supported by
Arm architecture.

Change-Id: Icf620b5039e45df6828d58fca089cad83b0bc669
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3): define SPMC manifest base address
feat(arm): add a macro for SPMC manifest base address
feat(rdv3): add carveout for BL32 image
feat(rdv3): introduce platform handler for Group0 interrupt
feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled
fix(neoverse-rd): set correct SVE vector lengths

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feat(arm): add a macro for SPMC manifest base address

In RESET_TO_BL31, the SPMC manifest base address that is utilized by
bl32_image_ep_info has to be statically defined as DT is not available.
Com

feat(arm): add a macro for SPMC manifest base address

In RESET_TO_BL31, the SPMC manifest base address that is utilized by
bl32_image_ep_info has to be statically defined as DT is not available.
Common arm code sets this to the top of SRAM using macros but it can be
different for some platforms. Hence, introduce the macro
PLAT_ARM_SPMC_MANIFEST_BASE that could be re-defined by platform as per
their use-case. Platforms that utilize arm_def.h would use the existing
value from arm common code.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I4491749ad2b5794e06c9bd11ff61e2e64f21a948

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Merge changes from topic "hm/heap-info" into integration

* changes:
fix(handoff): remove XFERLIST_TB_FW_CONFIG
feat(arm): migrate heap info to fw handoff
feat(mbedtls): introduce crypto lib he

Merge changes from topic "hm/heap-info" into integration

* changes:
fix(handoff): remove XFERLIST_TB_FW_CONFIG
feat(arm): migrate heap info to fw handoff
feat(mbedtls): introduce crypto lib heap info struct
feat(handoff): add Mbed-TLS heap info entry tag
refactor(arm): refactor secure TL initialization
fix(handoff): fix message formatting of hex values
feat(handoff): add func to check and init a tl
fix(arm): resolve dangling comments around macros

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refactor(arm): refactor secure TL initialization

The initialization logic for the secure transfer list is currently
scattered and duplicated across platform setup code. This not only leads
to ineffi

refactor(arm): refactor secure TL initialization

The initialization logic for the secure transfer list is currently
scattered and duplicated across platform setup code. This not only leads
to inefficiency but also complicates access to transfer lists from other
parts of the code without invoking setup functions. For instance,
arm_bl2_setup_next_ep_info acts as a thin wrapper in arm_bl2_setup.c to
provide access to the secure transfer list.

To streamline the interface, all setup code has been consolidated into a
central location.

Change-Id: I99d2a567ff39df88baa57e7e08607fccb8af189c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly r

fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly removed constraints on using HW_CONFIG with RESET_TO_BL2.

Change-Id: I19d61812fed6fa4b668875e5bf4eafd1a8a660f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "fix(arm): load dt before updating entry point" into integration

fix(arm): load dt before updating entry point

For firmware handoff, ensure the device tree (dt) is loaded into memory
before setting the entry point arguments for the next bootloader stage.
This all

fix(arm): load dt before updating entry point

For firmware handoff, ensure the device tree (dt) is loaded into memory
before setting the entry point arguments for the next bootloader stage.
This allows the dt to be found and its address passed as an argument.

Change-Id: Ifedd7c573e2d4f6d68c596907d9d6c6a3eded317
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow
feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3
feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

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feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

In the normal boot flow, BL2 sets up the Granule Protection Tables
(GPT). As BL2 is not a part of RESET_TO_BL31, BL31 needs to set up GPT
for

feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

In the normal boot flow, BL2 sets up the Granule Protection Tables
(GPT). As BL2 is not a part of RESET_TO_BL31, BL31 needs to set up GPT
for CPUs supporting FEAT_RME.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I9ad16bd93ea9fbad422dd56e2ba1d600a30eea30

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Merge changes from topic "hm/tlc" into integration

* changes:
feat(handoff): make tl generation flexible
feat(tlc): add command gen-header
feat(tlc): add support for tox
refactor(tlc): fix s

Merge changes from topic "hm/tlc" into integration

* changes:
feat(handoff): make tl generation flexible
feat(tlc): add command gen-header
feat(tlc): add support for tox
refactor(tlc): fix static check errors and code style

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feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.

Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "hm/handoff" into integration

* changes:
fix(arm): move HW_CONFIG relocation into BL31
feat: add option to input attr as string of flag names
feat: add option to input

Merge changes from topic "hm/handoff" into integration

* changes:
fix(arm): move HW_CONFIG relocation into BL31
feat: add option to input attr as string of flag names
feat: add option to input text instead of tag id number
feat: add creating transfer lists from yaml files

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Merge "fix(arm): correct the RESET_TO_BL31 x1 handoff arg" into integration

fix(arm): move HW_CONFIG relocation into BL31

Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in d

fix(arm): move HW_CONFIG relocation into BL31

Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in duplicate code in BL31 to cater for the `RESET_TO_BL31`
case. By moving the re-location logic to BL31, we simplify handling of
the non-secure DT and TL.

Change-Id: Id239f9410669afe4b223fa8d8bb093084a0e5e1b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(arm): correct the RESET_TO_BL31 x1 handoff arg

Use the designated macro to accurately set the signature within the
parameters transferred from BL33 to the non-secure payload.

Change-Id: Id91319

fix(arm): correct the RESET_TO_BL31 x1 handoff arg

Use the designated macro to accurately set the signature within the
parameters transferred from BL33 to the non-secure payload.

Change-Id: Id91319121a70b2c72f8489450f191ca4f129cfcb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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