| cd89a704 | 16-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(tc): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed
refactor(tc): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I645f6e8638cedfa6ff92d07b93cbaf38bdb2e09f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| a99a378d | 16-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signe
refactor(fvp): update RSS driver inteface calls
In order to comply with the previous RSS driver change,
interface calls have been updated.
Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| e87102f3 | 29-Jun-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "gr/cpu_rename" into integration
* changes:
chore: rename hayes to a520
chore: rename hunter to a720
chore: rename hunter_elp to cortex-x4 |
| dea3d71e | 28-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hayes to a520
Rename Cortex-hayes to Cortes-A520
Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 31b39455 | 23-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hunter to a720
Rename cortex_hunter to cortex_a720
Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 0bc2f3d2 | 29-Jun-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(fvp): adjust BL31 maximum size as per total SRAM size" into integration |
| 870fcb94 | 23-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hunter_elp to cortex-x4
Rename hunter_elp to cortex-x4
Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
| 24e224b4 | 27-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(fvp): adjust BL31 maximum size as per total SRAM size
Adjusted BL31 maximum size as per total SRAM size.
Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <M
fix(fvp): adjust BL31 maximum size as per total SRAM size
Adjusted BL31 maximum size as per total SRAM size.
Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 448d4d97 | 28-Jun-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration |
| e8947b27 | 23-Jun-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration |
| 6b6cefbf | 23-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "RAS_REFACTORING" into integration
* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memor
Merge changes from topic "RAS_REFACTORING" into integration
* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority
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| fa07049e | 22-Jun-2023 |
Daniel Boulby <daniel.boulby@arm.com> |
docs: remove deprecated tc0 from list of supported FVPs
TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.
Si
docs: remove deprecated tc0 from list of supported FVPs
TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc
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|
| 02886326 | 22-Jun-2023 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI hea
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI header to enable SDEI feature on RD-N2 platform.
- Add TZC configuration for CPER memory region for RD-N2 platform
variants. This region is marked for non-secure access as OSPM and
firmware need to access this region.
- Defines all base element RAM errors for RD-N2 platform variants.
- Defines a platform RAS event map and respective RAS config data
structure.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ideaed598f4924f3b9836d4d7e9ef76b9b7580b48
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| 80f8769b | 25-May-2023 |
Werner Lewis <werner.lewis@arm.com> |
fix(morello): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupt
fix(morello): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupts according to the Morello TRM and InfraSYSDESIGN4.0
specification.
Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I783a472d92601d86f1844f0d035dd0d036b2bfca
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|
| 0ad935f7 | 22-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "ffa_el3_spmc_fixes" into integration
* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve dir
Merge changes from topic "ffa_el3_spmc_fixes" into integration
* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve direct messaging validation
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|
| c040621d | 15-Nov-2022 |
Marc Bonnici <marc.bonnici@arm.com> |
fix(el3-spm): fix LSP direct message response
Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id
fix(el3-spm): fix LSP direct message response
Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I482c08d4657617adb00b0f3cf3c8ddc84f1bf7c8
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|
| 41e56f42 | 05-Jun-2023 |
Chris Kay <chris.kay@arm.com> |
feat(fvp): allow configurable FVP Trusted SRAM size
In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you t
feat(fvp): allow configurable FVP Trusted SRAM size
In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.
This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:
FVP_TRUSTED_SRAM_SIZE=384
This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.
Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 733cc2ad | 20-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(build): include Cortex-A78AE cpu file for FVP" into integration |
| 87259380 | 20-Jun-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I814cdadb,I429eb473,I441f9a60 into integration
* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
Merge changes I814cdadb,I429eb473,I441f9a60 into integration
* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID
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| 31f60a96 | 06-Jun-2023 |
sahil <sahil@arm.com> |
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across bot
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across both the chips.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I814cdadb59c8765c239ae0375e547718b7f208ff
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| ec8ba97e | 15-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
feat(juno): add mbedtls_asn1_get_len symbol in ROMlib
mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Ch
feat(juno): add mbedtls_asn1_get_len symbol in ROMlib
mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5609da000bbfc8a1503c298550ae3b0ba881fc96
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| 06050601 | 13-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib
mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Cha
feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib
mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I14310c80033a1142a94c0c4b54d63331479b643d
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| f4d011b0 | 12-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "psci-osi" into integration
* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p
Merge changes from topic "psci-osi" into integration
* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend
show more ...
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| ab23061e | 07-Jun-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "bk/clearups" into integration
* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control regist
Merge changes from topic "bk/clearups" into integration
* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control register setup section
chore(pauth): remove redundant pauth_disable_el3() call
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| e14b7acb | 06-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "refactor(fvp): nv ctr addr static helper function" into integration |