| 40111d44 | 14-Nov-2016 |
Soby Mathew <soby.mathew@arm.com> |
Add SCMI support for Juno platform
This patch adds the memory map region for the SCMI payload memory and maps the Juno core indices to SCMI power domains via the `plat_css_core_pos_to_scmi_dmn_id_ma
Add SCMI support for Juno platform
This patch adds the memory map region for the SCMI payload memory and maps the Juno core indices to SCMI power domains via the `plat_css_core_pos_to_scmi_dmn_id_map` array.
Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| e1c59ab3 | 06-Dec-2016 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Introduce ARM GIC-600 driver
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed t
Introduce ARM GIC-600 driver
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same.
The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600.
For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide.
Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| d40ab484 | 09-Nov-2016 |
David Wang <david.wang@arm.com> |
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardwa
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler.
Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 9bedc6d3 | 02-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Remove plat_match_rotpk reference
This function was removed long ago. Remove remaining pragma reference.
Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80 Signed-off-by: dp-arm <dimitris.papast
Remove plat_match_rotpk reference
This function was removed long ago. Remove remaining pragma reference.
Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
show more ...
|
| 0851cb24 | 02-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
fvp: Remove unnecessary default case
The default case is impossible to hit as the `power_level` is already checked earlier. Avoids a clang warning.
Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3
fvp: Remove unnecessary default case
The default case is impossible to hit as the `power_level` is already checked earlier. Avoids a clang warning.
Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3a8ab Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
show more ...
|
| e715e676 | 24-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #938 from masahir0y/tools_share
Collect headers shared between TF and host-tools into include/tools_share |
| 232c6b34 | 23-May-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
FVP,Juno: switch FVP and Juno to use generic TBBR OID header
The header tbbr_oid.h contains OIDs obtained by ARM Ltd. so there is no good reason to use platform_oid.h
Signed-off-by: Masahiro Yamada
FVP,Juno: switch FVP and Juno to use generic TBBR OID header
The header tbbr_oid.h contains OIDs obtained by ARM Ltd. so there is no good reason to use platform_oid.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| bb41eb7a | 22-May-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
cert: move platform_oid.h to include/tools_share for all platforms
Platforms aligned with TBBR are supposed to use their own OIDs, but defining the same macros with different OIDs does not provide a
cert: move platform_oid.h to include/tools_share for all platforms
Platforms aligned with TBBR are supposed to use their own OIDs, but defining the same macros with different OIDs does not provide any value (at least technically).
For easier use of TBBR, this commit allows platforms to reuse the OIDs obtained by ARM Ltd. This will be useful for non-ARM vendors that do not need their own extension fields in their certificate files.
The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h
Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the backward compatibility.
For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
show more ...
|
| 81602a97 | 22-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #939 from dp-arm/dp/AArch32_tbbr
Add TBBR and FWU support for AArch32 |
| 4fd4af26 | 16-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #942 from soby-mathew/sm/fix_juno_build_err
Juno: Fix AArch32 sp_min build |
| bbf4c22d | 16-May-2017 |
Soby Mathew <soby.mathew@arm.com> |
Juno: Fix AArch32 sp_min build
The commit abd2aba99ef108e0d0bb5d71c0b6e9c47ca26377 introduced a regression to the AArch32 sp_min Juno build. This patch fixes that.
Change-Id: I4b141717684d6aee60c76
Juno: Fix AArch32 sp_min build
The commit abd2aba99ef108e0d0bb5d71c0b6e9c47ca26377 introduced a regression to the AArch32 sp_min Juno build. This patch fixes that.
Change-Id: I4b141717684d6aee60c761ea17f23170aa6708c3 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| a4409008 | 15-Feb-2017 |
dp-arm <dimitris.papastamos@arm.com> |
AArch32: Add `TRUSTED_BOARD_BOOT` support
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode.
To build this patch the "mbedtls/include/mbedtls/bignum.h" needs to be modified to remove `#
AArch32: Add `TRUSTED_BOARD_BOOT` support
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode.
To build this patch the "mbedtls/include/mbedtls/bignum.h" needs to be modified to remove `#define MBEDTLS_HAVE_UDBL` when `MBEDTLS_HAVE_INT32` is defined. This is a workaround for "https://github.com/ARMmbed/mbedtls/issues/708"
NOTE: TBBR support on Juno AArch32 is not currently supported.
Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
show more ...
|
| 144c3f5e | 11-May-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
FVP: Break circular dependency in platform header files
We used to have the following circular dependency in the FVP platform header files:
+-> arm_def.h ---> platform_def.h ---> fvp_def.h --+ |_
FVP: Break circular dependency in platform header files
We used to have the following circular dependency in the FVP platform header files:
+-> arm_def.h ---> platform_def.h ---> fvp_def.h --+ |__________________________________________________|
This patch breaks it by not including 'arm_def.h' from 'fvp_def.h'.
Change-Id: I280d906559e3343dd38764029e77c0ea768b4fec Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| 82cb2c1a | 03-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Use SPDX license identifiers
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by
Use SPDX license identifiers
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
show more ...
|
| 0f22bef3 | 29-Apr-2017 |
Scott Branden <sbranden@users.noreply.github.com> |
Merge branch 'integration' into tf_issue_461 |
| 53d9c9c8 | 10-Apr-2017 |
Scott Branden <scott.branden@broadcom.com> |
Move defines in utils.h to utils_def.h to fix shared header compile issues
utils.h is included in various header files for the defines in it. Some of the other header files only contain defines. Th
Move defines in utils.h to utils_def.h to fix shared header compile issues
utils.h is included in various header files for the defines in it. Some of the other header files only contain defines. This allows the header files to be shared between host and target builds for shared defines.
Recently types.h has been included in utils.h as well as some function prototypes.
Because of the inclusion of types.h conflicts exist building host tools abd these header files now. To solve this problem, move the defines to utils_def.h and have this included by utils.h and change header files to only include utils_def.h and not pick up the new types.h being introduced.
Fixes ARM-software/tf-issues#461
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Remove utils_def.h from utils.h
This patch removes utils_def.h from utils.h as it is not required. And also makes a minor change to ensure Juno platform compiles.
Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29
show more ...
|
| abd2aba9 | 09-Dec-2016 |
Soby Mathew <soby.mathew@arm.com> |
CSS: Allow system suspend only via PSCI SYSTEM_SUSPEND API
The CSS power management layer previously allowed to suspend system power domain level via both PSCI CPU_SUSPEND and PSCI SYSTEM_SUSPEND AP
CSS: Allow system suspend only via PSCI SYSTEM_SUSPEND API
The CSS power management layer previously allowed to suspend system power domain level via both PSCI CPU_SUSPEND and PSCI SYSTEM_SUSPEND APIs. System suspend via PSCI CPU_SUSPEND was always problematic to support because of issues with targeting wakeup interrupts to suspended cores before the per-cpu GIC initialization is done. This is not the case for PSCI SYSTEM_SUSPEND API because all the other cores are expected to be offlined prior to issuing system suspend and PSCI CPU_ON explicit calls will be made to power them on. Hence the Juno platform used to downgrade the PSCI CPU_SUSPEND request for system power domain level to cluster level by overriding the default `plat_psci_pm_ops` exported by CSS layer.
Given the direction the new CSS platforms are evolving, it is best to limit the system suspend only via PSCI SYSTEM_SUSPEND API for all CSS platforms. This patch makes changes to allow system suspend only via PSCI SYSTEM_SUSPEND API. The override of `plat_psci_ops` for Juno is removed.
Change-Id: Idb30eaad04890dd46074e9e888caeedc50a4b533 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| 6f249345 | 14-Nov-2016 |
Yatharth Kochar <yatharth.kochar@arm.com> |
AArch32: Add SP_MIN support for JUNO
This patch adds support for SP_MIN on JUNO platform. The changes include addition of AArch32 assembly files, JUNO specific SP_MIN make file and miscellaneous cha
AArch32: Add SP_MIN support for JUNO
This patch adds support for SP_MIN on JUNO platform. The changes include addition of AArch32 assembly files, JUNO specific SP_MIN make file and miscellaneous changes in ARM platform files to enable support for SP_MIN.
Change-Id: Id1303f422fc9b98b9362c757b1a4225a16fffc0b Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
show more ...
|
| 07570d59 | 14-Nov-2016 |
Yatharth Kochar <yatharth.kochar@arm.com> |
Changes to support execution in AArch32 state for JUNO
Following steps are required to boot JUNO in AArch32 state: 1> BL1, in AArch64 state, loads BL2. 2> BL2, in AArch64 state, initializes DDR. L
Changes to support execution in AArch32 state for JUNO
Following steps are required to boot JUNO in AArch32 state: 1> BL1, in AArch64 state, loads BL2. 2> BL2, in AArch64 state, initializes DDR. Loads SP_MIN & BL33 (AArch32 executable)images. Calls RUN_IMAGE SMC to go back to BL1. 3> BL1 writes AArch32 executable opcodes, to load and branch at the entrypoint address of SP_MIN, at HI-VECTOR address and then request for warm reset in AArch32 state using RMR_EL3.
This patch makes following changes to facilitate above steps: * Added assembly function to carry out step 3 above. * Added region in TZC that enables Secure access to the HI-VECTOR(0xFFFF0000) address space. * AArch32 image descriptor is used, in BL2, to load SP_MIN and BL33 AArch32 executable images.
A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that controls above changes. By default this flag is disabled.
NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO.
Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
show more ...
|
| 3b68c09c | 06-Apr-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #888 from douglas-raillard-arm/dr/fix_ULL_issue
Fix ARM_BL31_IN_DRAM build |
| ed756252 | 06-Apr-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #886 from dp-arm/dp/stack-protector
Add support for GCC stack protection |
| f9608bc8 | 08-Mar-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
Fix ARM_BL31_IN_DRAM build
Some header files using the ULL() macro were not directly including utils.h where the macro definition resides. As a consequence, a linker script with values using this ma
Fix ARM_BL31_IN_DRAM build
Some header files using the ULL() macro were not directly including utils.h where the macro definition resides. As a consequence, a linker script with values using this macro did not see the macro definition and kept the "ULL(<value>)" call in the preprocessed file, which lead to link error.
Files using ULL() macro now include utils.h directly.
Change-Id: I433a7f36bd21a156c20e69bc2a2bb406140ebdf9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
show more ...
|
| e6d2aea1 | 28-Feb-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Juno: Initialize stack protector canary from the trusted entropy source
Change-Id: I7f3e4bfd46613c6311ba4015d56705414fd6feab Signed-off-by: dp-arm <dimitris.papastamos@arm.com> |
| df9a39ea | 27-Feb-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Juno: Introduce juno_getentropy(void *buf, size_t len)
This function fills the buffer (first argument) with the specified number of bytes (second argument) from the trusted entropy source.
This fun
Juno: Introduce juno_getentropy(void *buf, size_t len)
This function fills the buffer (first argument) with the specified number of bytes (second argument) from the trusted entropy source.
This function will be used to initialize the stack protector canary.
Change-Id: Iff15aaf4778c13fa883ecb5528fcf9b8479d4489 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
show more ...
|
| 51faada7 | 24-Feb-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
Add support for GCC stack protection
Introduce new build option ENABLE_STACK_PROTECTOR. It enables compilation of all BL images with one of the GCC -fstack-protector-* options.
A new platform funct
Add support for GCC stack protection
Introduce new build option ENABLE_STACK_PROTECTOR. It enables compilation of all BL images with one of the GCC -fstack-protector-* options.
A new platform function plat_get_stack_protector_canary() is introduced. It returns a value that is used to initialize the canary for stack corruption detection. Returning a random value will prevent an attacker from predicting the value and greatly increase the effectiveness of the protection.
A message is printed at the ERROR level when a stack corruption is detected.
To be effective, the global data must be stored at an address lower than the base of the stacks. Failure to do so would allow an attacker to overwrite the canary as part of an attack which would void the protection.
FVP implementation of plat_get_stack_protector_canary is weak as there is no real source of entropy on the FVP. It therefore relies on a timer's value, which could be predictable.
Change-Id: Icaaee96392733b721fa7c86a81d03660d3c1bc06 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
show more ...
|