feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by n

feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by normal world.
For this, add last 2MB area of norflash0 in TZC setting.

Change-Id: Ice63f13c34f452f2b8cb93ee88dc666632b84248
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

T

feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

The only exception to this are older secure world dispatchers, which
assume that a CPU_SUSPEND call will be terminal and therefore can
clobber context. This was patched over in common code and hidden behind
a flag. This patch moves this to the dispatchers themselves.

Dispatchers that don't register svc_suspend{_finish} are unaffected.
Those that do must save the NS context before clobbering it and
restoring in only in case of a pabandon. Due to this operation being
non-trivial, this patch makes the assumption that these dispatchers will
only be present on hardware that does not support pabandon and therefore
does not add any contexting for them. In case this assumption ever
changes, asserts are added that should alert us of this change.

Change-Id: I94a907515b782b4d2136c0d274246cfe1d567c0e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not

refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not
entirely correct, ways - one is missing a dependency to the makefiles,
another generates its .d inline, and the prints are different. That has
resulted in platforms reimplementing this functionality, making the
build brittle - a change to the overall build system doesn't propagate.
So add a MAKE_PRE macro that will make a rule with all the bells and
whistles to run the preprocessor on an arbitrary file.

This patch converts the arm platforms' cot_descriptors DTS rules. The
files are renamed to fit with the build rule and all extra flags are
dropped. Those flags are only necessary for building BL2 c files, which
will be passed to the output C file. Only the DTS flags are needed for
the preprocessing step, which will be passed automatically.

Change-Id: I3c1cc0ecf93b87d828f868214928c1bc9bcb5758
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MP

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)

TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)

Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3

Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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feat(build): put crttool in the build directory

Same as fiptool. Move all artefacts to the platform build directory and
convert to the standard build macro to make things more generic. Leave
a symli

feat(build): put crttool in the build directory

Same as fiptool. Move all artefacts to the platform build directory and
convert to the standard build macro to make things more generic. Leave
a symlink for the final binary in case someone depends on it.

Change-Id: I82ef846a95474ba385377032fb185e548827bf5c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "build(handoff)!: switch to LibTL submodule" into integration

feat(tc): add support for configuring DSU settings

This patch allows tc platforms to update DSU
CLUSTERPWRDN_EL1 and CLUSTERPWRCTLR_EL1 settings.
TC22 and TC23 use the DSU-120. Currently
we use the

feat(tc): add support for configuring DSU settings

This patch allows tc platforms to update DSU
CLUSTERPWRDN_EL1 and CLUSTERPWRCTLR_EL1 settings.
TC22 and TC23 use the DSU-120. Currently
we use the reset values as default settings as
per the DSU-120 TRM.

Reference: https://developer.arm.com/documentation/102547/0201

Change-Id: I48e0b5bd5881612e9b8b804948260f69c25c34d9
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

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build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): implement platform API for load and auth image

Introduce and implement a stub implementation of
`plat_lfa_load_auth_image()` for the FVP platform. For AEM FVP, no
actual image loading or

feat(fvp): implement platform API for load and auth image

Introduce and implement a stub implementation of
`plat_lfa_load_auth_image()` for the FVP platform. For AEM FVP, no
actual image loading or authentication is required as of now, as
images are assumed to be pre-loaded and authenticated.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I82e51f5d18db6d5b9c61f9081b451619d761abe8

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feat(fvp): implement platform API for LFA cancel operation

Introduce and implement a stub implementation of `plat_lfa_cancel()`
for the FVP platform. This function will later be expanded to handle
c

feat(fvp): implement platform API for LFA cancel operation

Introduce and implement a stub implementation of `plat_lfa_cancel()`
for the FVP platform. This function will later be expanded to handle
component-specific LFA cancellation logic.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9690b011313bbe0fd458cbe47f32445f8d2d79fa

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feat(fvp): implement platform API for LFA activation pending check

Introduce and implement `is_plat_lfa_activation_pending()' API for the
FVP platform. Currently, only the RMM component is marked as

feat(fvp): implement platform API for LFA activation pending check

Introduce and implement `is_plat_lfa_activation_pending()' API for the
FVP platform. Currently, only the RMM component is marked as pending.

Change-Id: I6cc84c65ba5fe1b47cc65cbeeb349aac9235533a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): initialize LFA component activators in platform layer

Update the FVP platform's LFA component table to populate the
'activator' and 'activation_pending' by introducing fields
in plat_lfa_

feat(fvp): initialize LFA component activators in platform layer

Update the FVP platform's LFA component table to populate the
'activator' and 'activation_pending' by introducing fields
in plat_lfa_component_info_t.
- 'activator': function pointers for component-specific
activation logic
- 'activation_pending': tracks whether the component's activation
is pending

Set the activator function pointers for supported components:
- BL31 via get_bl31_activator()
- RMM (if RME is enabled) via get_rmm_activator()

This allows the LFA service to invoke component-specific prime
and activate callbacks through platform-registered hooks.

Change-Id: Ifd997a8b8cab209c25aabb2e9d4eab59e909ea4d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): implement LFA get components API

Introduce platform-specific implementation of
`plat_lfa_get_components()` for the Arm FVP platform. This function
returns LFA component metadata, includin

feat(fvp): implement LFA get components API

Introduce platform-specific implementation of
`plat_lfa_get_components()` for the Arm FVP platform. This function
returns LFA component metadata, including component ID, UUID for
each supported firmware image and number of components.

Change-Id: I9e7cbce5865becf3e4babcb770bc5eb3b69a0be8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5

Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5): probe components
feat(gicv5): initialise the IWB
feat(gicv5): initialise the IRS
feat(gicv5): assign interrupt sources to appropriate security states
feat(gicv5): add a barebones GICv5 driver
feat(gicv5): add support for building with gicv5

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docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
curren

docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
current limitations and known constraints.

Introduce build-time checks to ensure incompatible configurations
(e.g., with SPMD or RMMD) fail early with a clear error message.

Initial GICv5 support in FVP is intended to facilitate early Linux
kernel bring-up and to assist with upstream kernel patch development.

Note: This patch is a temporary measure and should be reverted once
proper and complete GICv5 support is upstreamed in TF-A.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2af839aec600040dfde75d74d02eff5a57ecda4e

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feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5 as the bindings are completely different.

This patch does not include a device tree. This will be added at a later
date.

Change-Id: Ifd0c7b4e0bc2ea1e53a6779ab4c50c4aec39dafb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(fvp): workaround when PCIe 2 region is not present in DTB" into integration

fix(fvp): workaround when PCIe 2 region is not present in DTB

This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
th

fix(fvp): workaround when PCIe 2 region is not present in DTB

This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
there are 2 PCIe regions but the upstream FVP DT sourced from
kernel.org does not have this region specified. Temporarily
workaround this issue in FVP platform layer till the upstream DT is
fixed.

Note that the DT in `fdts` folder of TF-A source tree already has the
2 regions specified.

[1] https://developer.arm.com/documentation/100966/1101-00/Programming-Reference-for-Base-FVPs/Base---memory

Change-Id: If220e2dbeff00a1bf6eccadbb0ebb661b9c5e529
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Add a new variable that can be optionally set when calling `make`
to allow hw_config (such as DTB) to exist at a specified address.
Prior to this chan

feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Add a new variable that can be optionally set when calling `make`
to allow hw_config (such as DTB) to exist at a specified address.
Prior to this change, the location was hardcoded to 0x82000000, which
could be overwritten if a preceeding image is large enough.
This new variable acts such that if it is unset, the behaviour
is exactly as before this patch, and if it is set, then the value
given is the hw-config's secondary-load-address value in the
fvp_fw_config DT.

Change-Id: I0b5158ef8c089b04078f2e9bb4408f03107591a5
Signed-off-by: emily.boarer@arm.com

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fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()

The function is called from assembly language before the stack is set
up. This fix prevents accessing unmapped memory at 0xffffffff

fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available()

The function is called from assembly language before the stack is set
up. This fix prevents accessing unmapped memory at 0xffffffff_ffffffxx
by not storing the midr_no_cpupwrctl array on the stack.

Change-Id: I920e32c34bddf86a1dbf05b7115026413483b3c1
Signed-off-by: Linus Nielsen <linus@haxx.se>

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Merge "chore(fvp): remove unused macro definition" into integration

fix(fvp): increase EventLog size for OP-TEE with multiple SPs

When OP-TEE runs with multiple Secure Partitions (SPs), a larger
EventLog size is required to accommodate the additional measurements.
T

fix(fvp): increase EventLog size for OP-TEE with multiple SPs

When OP-TEE runs with multiple Secure Partitions (SPs), a larger
EventLog size is required to accommodate the additional measurements.
This patch updates the configuration to allocate sufficient memory
in such cases.

In the future, the Maximum EventLog size should be calculated based
on the maximum number of images loaded by BL2. That enhancement can
be addressed in a separate patch.

Change-Id: Ibd9bed0a5b1029158142711fd08809729dd05b08
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): increase BL1 RW for PSA Crypto

Increase BL1 RW for PSA Crypto due to PSA key ID management redesign
needing an increase in heap size.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeiste

feat(fvp): increase BL1 RW for PSA Crypto

Increase BL1 RW for PSA Crypto due to PSA key ID management redesign
needing an increase in heap size.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7c8d009f244be6252eff0d3ded3f1ca83fb1de21

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chore(fvp): remove unused macro definition

Remove an unused macro from the FVP platform code to
reduce clutter.

Change-Id: I88f9b3e6567362c0559fa58e1fbf9ace49c986b6
Signed-off-by: Manish V Badarkhe

chore(fvp): remove unused macro definition

Remove an unused macro from the FVP platform code to
reduce clutter.

Change-Id: I88f9b3e6567362c0559fa58e1fbf9ace49c986b6
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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