| ae030052 | 16-Mar-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "od/ffa_spmc_pwr" into integration
* changes:
SPM: declare third cactus instance as UP SP
SPMD: lock the g_spmd_pm structure
FF-A: implement FFA_SECONDARY_EP_REGISTER |
| e96fc8e7 | 11-Feb-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
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| 72bdcb9a | 29-Jan-2021 |
Usama Arif <usama.arif@arm.com> |
plat: tc0: add matterhorn_elp_arm library to tc0
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf |
| 8ef06b6c | 02-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu CPU lib" into integration |
| aaabf978 | 15-Oct-2020 |
johpow01 <john.powell@arm.com> |
Add Makalu CPU lib
Add basic support for Makalu CPU.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d |
| cb5f0faa | 07-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
Now that we have a framework for the SMCCC TRNG interface, and the
existing Juno entropy code has been prepared, add the few remainin
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
Now that we have a framework for the SMCCC TRNG interface, and the
existing Juno entropy code has been prepared, add the few remaining bits
to implement this interface for the Juno Trusted Entropy Source.
We retire the existing Juno specific RNG interface, and use the generic
one for the stack canary generation.
Change-Id: Ib6a6e5568cb8e0059d71740e2d18d6817b07127d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| eb18ce32 | 16-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
plat/arm: juno: Condition Juno entropy source with CRC instructions
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.
To improve th
plat/arm: juno: Condition Juno entropy source with CRC instructions
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.
To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.
This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.
Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| d3e145b4 | 11-Feb-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "plat/arm: juno: Refactor juno_getentropy()" into integration |
| b2e5e56f | 11-Feb-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat/arm/rdn2: update TZC base address" into integration |
| edbe490b | 11-Feb-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "morello: Modify morello_plat_info structure" into integration |
| 543f0d8b | 07-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
plat/arm: juno: Refactor juno_getentropy()
Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we w
plat/arm: juno: Refactor juno_getentropy()
Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we will actually only ever request 16 bytes, as this is what
the hardware implements. Out of this, we only need at most 64 bits for
the canary.
In preparation for the introduction of the SMCCC TRNG interface, we
can simplify this Juno specific interface by making it compatible with
the generic one: We just deliver 64 bits of entropy on each call.
This reduces the complexity of the code. As the raw entropy register
readouts seem to be biased, it makes sense to do some conditioning
inside the juno_getentropy() function already.
Also initialise the TRNG hardware, if not already done.
Change-Id: I11b977ddc5417d52ac38709a9a7b61499eee481f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 4e8060d2 | 04-Feb-2021 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/rdn2: update TZC base address
Update TZC base address to align with the recent changes in the platform
memory map.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.c
plat/arm/rdn2: update TZC base address
Update TZC base address to align with the recent changes in the platform
memory map.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a
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| f98630fb | 24-Jan-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat/arm: fvp: Protect GICR frames for fused/unused cores
Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.
This opens up the security hole where the active c
plat/arm: fvp: Protect GICR frames for fused/unused cores
Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.
This opens up the security hole where the active core can write
the GICR frame of fused/inactive core. To avoid this issue, disable
the GICR frame of all inactive cores as below:
1. After primary CPU boots up, map GICR region of all cores as
read-only.
2. After primary CPU boots up, map its GICR region as read-write
and initialize its redistributor interface.
3. After secondary CPU boots up, map its GICR region as read-write
and initialize its redistributor interface.
4. All unused/fused core's redistributor regions remain read-only and
write attempt to such protected regions results in an exception.
As mentioned above, this patch offers only the GICR memory-mapped
region protection considering there is no facility at the GIC IP
level to avoid writing the redistributor area.
These changes are currently done in BL31 of Arm FVP and guarded under
the flag 'FVP_GICR_REGION_PROTECTION'.
As of now, this patch is tested manually as below:
1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core.
2. Verify data abort triggered by manually updating the ‘GICR_CTLR’
register of core 1’s(fused) redistributor from core 0(active).
Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| e0cea783 | 23-Jan-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
plat/arm: fvp: Do not map GIC region in BL1 and BL2
GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memor
plat/arm: fvp: Do not map GIC region in BL1 and BL2
GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memory regions in the
future.
Retains mapping of CCN interconnect region in BL1 and BL2
overlapped with the GIC memory region.
Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 42ea8d67 | 20-Jan-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
morello: Modify morello_plat_info structure
The structure has been modified to specify the memory
size in bytes instead of Gigabytes.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by
morello: Modify morello_plat_info structure
The structure has been modified to specify the memory
size in bytes instead of Gigabytes.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I3384677d79af4f3cf55d3c353b6c20bb827b5ae7
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| 041d7c7b | 27-Jan-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
rainier: remove cpu workaround for errata 1542419
This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.
Change-Id: Icaca299b13ef83
rainier: remove cpu workaround for errata 1542419
This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.
Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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| d5105d99 | 03-Feb-2021 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "RD_INFRA_POWER_MODING" into integration
* changes:
plat/arm/board: enable AMU for RD-N2
plat/arm/board: enable AMU for RD-V1
plat/arm/sgi: allow all PSCI callbacks on
Merge changes from topic "RD_INFRA_POWER_MODING" into integration
* changes:
plat/arm/board: enable AMU for RD-N2
plat/arm/board: enable AMU for RD-V1
plat/arm/sgi: allow all PSCI callbacks on RD-V1
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| 6d0dcc7d | 03-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat/arm:juno: fix parallel build issue for romlib config" into integration |
| e5da15e0 | 28-Oct-2020 |
Avinash Mehta <avinash.mehta@arm.com> |
product/tc0: Enable Theodul DSU in TC platform
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
product/tc0: Enable Theodul DSU in TC platform
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
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| 5e508f06 | 02-Feb-2021 |
Zelalem <zelalem.aweke@arm.com> |
plat/arm:juno: fix parallel build issue for romlib config
When building TF-A with USE_ROMLIB=1 and -j make options, the build fails with the following error:
make[1]: *** No rule to make target '/bu
plat/arm:juno: fix parallel build issue for romlib config
When building TF-A with USE_ROMLIB=1 and -j make options, the build fails with the following error:
make[1]: *** No rule to make target '/build/juno/debug/romlib/romlib.bin', needed by 'bl1_romlib.bin'.
This patch fixes that issue.
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: I0cca416f3f50f400759164e0735c2d6b520ebf84
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| f7bab276 | 27-Jan-2021 |
Pranav Madhu <pranav.madhu@arm.com> |
plat/arm/board: enable AMU for RD-N2
AMU counters are used for monitoring the CPU performance. RD-N2 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for
plat/arm/board: enable AMU for RD-N2
AMU counters are used for monitoring the CPU performance. RD-N2 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).
Change-Id: I5cc749cf63c18fc5c7563dd754c2f42990a97e23
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| c9bf2cf5 | 11-Nov-2020 |
Pranav Madhu <pranav.madhu@arm.com> |
plat/arm/board: enable AMU for RD-V1
AMU counters are used for monitoring the CPU performance. RD-V1 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for
plat/arm/board: enable AMU for RD-V1
AMU counters are used for monitoring the CPU performance. RD-V1 platform
has architected AMU available for each core. Enable the use of AMU by
non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).
Change-Id: I4003d21407953f65b3ce99eaa8f496d6052546e0
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 036e9c17 | 25-Jan-2021 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes I635cf82e,Iee3b4e0d into integration
* changes:
Makefile: Fix ${FIP_NAME} to be rebuilt only when needed
Makefile: Do not mark file targets as .PHONY target |
| 90aecf1e | 15-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm: rename rddanielxlr to rdv1mc
Reference Design platform RD-Daniel-ConfigXLR has been renamed to
RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace
it with 'rdv1mc' wher
plat/arm: rename rddanielxlr to rdv1mc
Reference Design platform RD-Daniel-ConfigXLR has been renamed to
RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace
it with 'rdv1mc' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I5d91c69738397b19ced43949b4080c74678e604c
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| edf771a1 | 15-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm: rename rddaniel to rdv1
Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.
Signed-
plat/arm: rename rddaniel to rdv1
Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I1702bab39c501f8c0a09df131cb2394d54c83bcf
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