| 90aecf1e | 15-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm: rename rddanielxlr to rdv1mc
Reference Design platform RD-Daniel-ConfigXLR has been renamed to
RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace
it with 'rdv1mc' wher
plat/arm: rename rddanielxlr to rdv1mc
Reference Design platform RD-Daniel-ConfigXLR has been renamed to
RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace
it with 'rdv1mc' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I5d91c69738397b19ced43949b4080c74678e604c
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|
| edf771a1 | 15-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm: rename rddaniel to rdv1
Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.
Signed-
plat/arm: rename rddaniel to rdv1
Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I1702bab39c501f8c0a09df131cb2394d54c83bcf
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|
| a9812206 | 24-Nov-2020 |
Pali Rohár <pali@kernel.org> |
Makefile: Do not mark file targets as .PHONY target
Only non-file targets should be set a .PHONY. Otherwise if file target is
set as .PHONY then targets which depends on those file .PHONY targets wo
Makefile: Do not mark file targets as .PHONY target
Only non-file targets should be set a .PHONY. Otherwise if file target is
set as .PHONY then targets which depends on those file .PHONY targets would
be always rebuilt even when their prerequisites are not changed.
File target which needs to be always rebuilt can be specified in Make
system via having a prerequisite on some .PHONY target, instead of marking
whole target as .PHONY. In Makefile projects it is common to create empty
.PHONY target named FORCE for this purpose.
This patch changes all file targets which are set as .PHONY to depends on
new .PHONY target FORCE, to ensure that these file targets are always
rebuilt (as before). Basically they are those targets which calls external
make subprocess.
After FORCE target is specified in main Makefile, remove it from other
Makefile files to prevent duplicate definitions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee3b4e0de93879b95eb29a1745a041538412e69e
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|
| 669ee776 | 21-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_C
Merge changes from topic "tc0_optee_sp" into integration
* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_CONFIG
plat: tc0: enable opteed support
plat: arm: Increase SP max size
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|
| fb86e537 | 15-Dec-2020 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/rdn2: update gic redistributor base address
RD-N2 platform has been updated to use six GIC ITS blocks. This results
in change in base address of the GIC Redistributor to accomodate two
new
plat/arm/rdn2: update gic redistributor base address
RD-N2 platform has been updated to use six GIC ITS blocks. This results
in change in base address of the GIC Redistributor to accomodate two
new GIC ITS blocks. Update the base address of GICR to reflect the same.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c
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|
| 39460d05 | 17-Nov-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2
- create SPMC manifest file with OP-TEE as SP
- add support for ARM_SPMC_MANIFEST_DTS build option
- add optee entry with ffa as method in tc0.dts
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
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|
| 86069c0c | 17-Nov-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: enable opteed support
Enable SPD=opteed support for tc0 platform.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ieb038d645c68fbe6b5a211c7279569e21b476fc3 |
| bd054fd6 | 11-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in mem
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in memory map
plat/arm/sgi: add platform id value for rdn2 platform
plat/arm/sgi: platform definitions for upcoming platforms
plat/arm/sgi: refactor header file inclusions
plat/arm/sgi: refactor the inclusion of memory mapping
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|
| 34e443e2 | 19-Nov-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
board/rdn2: add board support for rdn2 platform
Add the initial board support for RD-N2 platform.
Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@ar
board/rdn2: add board support for rdn2 platform
Add the initial board support for RD-N2 platform.
Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| 60f995fd | 18-Nov-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm/sgi: refactor header file inclusions
Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support
plat/arm/sgi: refactor header file inclusions
Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.
Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| db2aeddc | 18-Nov-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm/sgi: refactor the inclusion of memory mapping
Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
us
plat/arm/sgi: refactor the inclusion of memory mapping
Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.
Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| 89832ac9 | 25-Nov-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
spm: provide number of vCPUs and VM size for first SP
The primary VM concept is removed from the SPMC.
Update the SPMC manifests with number of Execution Contexts
and SP workspace size for the first
spm: provide number of vCPUs and VM size for first SP
The primary VM concept is removed from the SPMC.
Update the SPMC manifests with number of Execution Contexts
and SP workspace size for the first Secure Partition (as it
is done for NWd secondary VMs and other SPs).
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3b9c52666f7dfe74ab1f7d2148ad0070ee44b54e
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|
| 5134fcbb | 24-Nov-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
spm: remove chosen node from SPMC manifests
The chosen node is no longer required as the SPMC implements
a specific boot flow which no longer requires this node.
Signed-off-by: Olivier Deprez <oliv
spm: remove chosen node from SPMC manifests
The chosen node is no longer required as the SPMC implements
a specific boot flow which no longer requires this node.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib566b602a7f83003a1b2d0ba5f6ebf4d8b7a9156
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|
| 76d22f06 | 03-Dec-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
spm: move OP-TEE SP manifest DTS to FVP platform
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0981c43e2ef8172138f65d95eac7b20f8969394e |
| b635d11b | 10-Nov-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
spm: remove device-memory node from SPMC manifests
The PVM concept is removed from the SPMC so the device-memory
node which is specifying the device memory range for the PVM
is no longer applicable.
spm: remove device-memory node from SPMC manifests
The PVM concept is removed from the SPMC so the device-memory
node which is specifying the device memory range for the PVM
is no longer applicable.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If0cb956e0197028b24ecb78952c66ec454904516
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|
| 25bbbd2d | 23-Oct-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
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|
| 00ad74c7 | 26-Oct-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "SPMC: adjust device region for first secure partition" into integration |
| d0d63afe | 08-Oct-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMC: adjust device region for first secure partition
For the first partition, mark first 2GB as device memory excluding
the Trusted DRAM region reserved for the SPMC.
Signed-off-by: Olivier Deprez
SPMC: adjust device region for first secure partition
For the first partition, mark first 2GB as device memory excluding
the Trusted DRAM region reserved for the SPMC.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b
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|
| 879b5b8b | 26-Aug-2020 |
Usama Arif <usama.arif@arm.com> |
plat: tc0: Configure TZC with secure world regions
This includes configuration for SPMC and trusted OS.
Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3
Signed-off-by: Usama Arif <usama.arif@ar
plat: tc0: Configure TZC with secure world regions
This includes configuration for SPMC and trusted OS.
Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3
Signed-off-by: Usama Arif <usama.arif@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
show more ...
|
| b0d12751 | 22-Sep-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: Enable SPMC execution at S-EL2
This patch enables SPMC execution at S-EL2 by adding below changes
- Map TC0_MAP_TZC_DRAM1 for loading SPMC
- Add details of cactus test secure par
plat: tc0: Enable SPMC execution at S-EL2
This patch enables SPMC execution at S-EL2 by adding below changes
- Map TC0_MAP_TZC_DRAM1 for loading SPMC
- Add details of cactus test secure partitions
- Adds tc0 spmc manifest file with details on secure partitions
- Inlcude TOS_FW_CONFIG when SPM is spmd
- Increases bl2 image size
SPMC at S-EL2 is only enabled when build with SPD=spmd.
Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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|
| a3ecbb35 | 22-Sep-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id
plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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|
| d32113c7 | 27-Jul-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled
To support platforms without Trusted DRAM this patch defines
PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM
plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled
To support platforms without Trusted DRAM this patch defines
PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or
DRAM region behind TZC.
Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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|
| c398caf5 | 28-May-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
plat: tc0: Disable SPE
Statistical Profiling Extension is not supported by Matterhorn core
Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d
Signed-off-by: Arunachalam Ganapathy <arunachalam.gan
plat: tc0: Disable SPE
Statistical Profiling Extension is not supported by Matterhorn core
Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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|
| 831b0e98 | 05-Aug-2020 |
Jimmy Brisson <jimmy.brisson@arm.com> |
Don't return error information from console_flush
And from crash_console_flush.
We ignore the error information return by console_flush in _every_
place where we call it, and casting the return typ
Don't return error information from console_flush
And from crash_console_flush.
We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.
Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
show more ...
|
| a4fdb893 | 06-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration
* changes:
Rename Neoverse Zeus to Neoverse V1
Rename Cortex Hercules AE to Cortex 78 AE |