1# 2# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Include GICv2 driver files 8include drivers/arm/gic/v2/gicv2.mk 9 10JUNO_GIC_SOURCES := ${GICV2_SOURCES} \ 11 plat/common/plat_gicv2.c \ 12 plat/arm/common/arm_gicv2.c 13 14JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 15 plat/arm/common/arm_cci.c 16 17JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 18 plat/arm/board/juno/juno_security.c \ 19 plat/arm/board/juno/juno_trng.c \ 20 plat/arm/common/arm_tzc400.c 21 22ifneq (${ENABLE_STACK_PROTECTOR}, 0) 23JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 24endif 25 26# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 27# SCP during power management operations and for SCP RAM Firmware transfer. 28CSS_USE_SCMI_SDS_DRIVER := 1 29 30PLAT_INCLUDES := -Iplat/arm/board/juno/include 31 32PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 33 plat/arm/board/juno/juno_common.c 34 35# Flag to enable support for AArch32 state on JUNO 36JUNO_AARCH32_EL3_RUNTIME := 0 37$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 38$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 39 40# Flag to enable support for TZMP1 on JUNO 41JUNO_TZMP1 := 0 42$(eval $(call assert_boolean,JUNO_TZMP1)) 43ifeq (${JUNO_TZMP1}, 1) 44$(eval $(call add_define,JUNO_TZMP1)) 45endif 46 47ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 48# Include BL32 in FIP 49NEED_BL32 := yes 50# BL31 is not required 51override BL31_SOURCES = 52 53# The BL32 needs to be built separately invoking the AARCH32 compiler and 54# be specifed via `BL32` build option. 55 ifneq (${ARCH}, aarch32) 56 override BL32_SOURCES = 57 endif 58endif 59 60ifeq (${ARCH},aarch64) 61BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 62 lib/cpus/aarch64/cortex_a57.S \ 63 lib/cpus/aarch64/cortex_a72.S \ 64 plat/arm/board/juno/juno_err.c \ 65 plat/arm/board/juno/juno_bl1_setup.c \ 66 drivers/arm/sp805/sp805.c \ 67 ${JUNO_INTERCONNECT_SOURCES} \ 68 ${JUNO_SECURITY_SOURCES} 69 70BL2_SOURCES += drivers/arm/sp805/sp805.c \ 71 lib/utils/mem_region.c \ 72 plat/arm/board/juno/juno_err.c \ 73 plat/arm/board/juno/juno_bl2_setup.c \ 74 plat/arm/common/arm_nor_psci_mem_protect.c \ 75 ${JUNO_SECURITY_SOURCES} 76 77BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 78 79BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 80 lib/cpus/aarch64/cortex_a53.S \ 81 lib/cpus/aarch64/cortex_a57.S \ 82 lib/cpus/aarch64/cortex_a72.S \ 83 lib/utils/mem_region.c \ 84 plat/arm/board/juno/juno_pm.c \ 85 plat/arm/board/juno/juno_topology.c \ 86 plat/arm/common/arm_nor_psci_mem_protect.c \ 87 ${JUNO_GIC_SOURCES} \ 88 ${JUNO_INTERCONNECT_SOURCES} \ 89 ${JUNO_SECURITY_SOURCES} 90 91ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 92BL1_SOURCES += drivers/arm/css/sds/sds.c 93endif 94 95ifeq (${TRUSTED_BOARD_BOOT}, 1) 96BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 97BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 98endif 99 100endif 101 102ifneq (${RESET_TO_BL31},0) 103 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 104 Please set RESET_TO_BL31 to 0.") 105endif 106 107ifeq ($(USE_ROMLIB),1) 108all : bl1_romlib.bin 109endif 110 111bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin romlib.bin 112 @echo "Building combined BL1 and ROMLIB binary for Juno $@" 113 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 114 115# Errata workarounds for Cortex-A53: 116ERRATA_A53_819472 := 1 117ERRATA_A53_824069 := 1 118ERRATA_A53_826319 := 1 119ERRATA_A53_827319 := 1 120ERRATA_A53_835769 := 1 121ERRATA_A53_836870 := 1 122ERRATA_A53_843419 := 1 123ERRATA_A53_855873 := 1 124 125# Errata workarounds for Cortex-A57: 126ERRATA_A57_806969 := 0 127ERRATA_A57_813419 := 1 128ERRATA_A57_813420 := 1 129ERRATA_A57_814670 := 1 130ERRATA_A57_817169 := 1 131ERRATA_A57_826974 := 1 132ERRATA_A57_826977 := 1 133ERRATA_A57_828024 := 1 134ERRATA_A57_829520 := 1 135ERRATA_A57_833471 := 1 136ERRATA_A57_859972 := 0 137 138# Errata workarounds for Cortex-A72: 139ERRATA_A72_859971 := 0 140 141# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 142# power down sequence 143SKIP_A57_L1_FLUSH_PWR_DWN := 1 144 145# Do not enable SVE 146ENABLE_SVE_FOR_NS := 0 147 148# Enable the dynamic translation tables library. 149ifeq (${ARCH},aarch32) 150 ifeq (${RESET_TO_SP_MIN},1) 151 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 152 endif 153else 154 ifeq (${RESET_TO_BL31},1) 155 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 156 endif 157endif 158 159ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 160 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 161 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 162 else 163 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 164 endif 165endif 166 167BL1_CPPFLAGS += -march=armv8-a+crc 168BL2_CPPFLAGS += -march=armv8-a+crc 169BL2U_CPPFLAGS += -march=armv8-a+crc 170BL31_CPPFLAGS += -march=armv8-a+crc 171BL32_CPPFLAGS += -march=armv8-a+crc 172 173# Add the FDT_SOURCES and options for Dynamic Config 174FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 175 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts 176 177FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 178TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 179 180# Add the FW_CONFIG to FIP and specify the same to certtool 181$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 182# Add the TB_FW_CONFIG to FIP and specify the same to certtool 183$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 184 185include plat/arm/board/common/board_common.mk 186include plat/arm/common/arm_common.mk 187include plat/arm/soc/common/soc_css.mk 188include plat/arm/css/common/css_common.mk 189