fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add th

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add the device memory used in the tf-a-tests to the SPMC
manifests.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I47376e67c700705d12338d7078292618a15d5546

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refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(arm): remove unused SP_MIN UART macros

Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, a

refactor(arm): remove unused SP_MIN UART macros

Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, and the macros are no longer used.

Therefore, this patch removes these unused UART macros.

Change-Id: I496349f876ba918fcafa7ed6c65d149914762290
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(tc): do not use r0 for HW_CONFIG" into integration

fix(tc): do not use r0 for HW_CONFIG

populate_next_bl_params_config already configures the register values
to be passed to BL33 and puts the HW_CONFIG address in r1. Therefore,
we do not need to ove

fix(tc): do not use r0 for HW_CONFIG

populate_next_bl_params_config already configures the register values
to be passed to BL33 and puts the HW_CONFIG address in r1. Therefore,
we do not need to override r0 here and should instead use r1 in BL33.

Change-Id: I00b425301957b5b0510416e1fa1f3599c0359bfc
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): group components into certificates

Set the cert_id argument to group the components
into certificates. The grouping reflects the likely units
of updateability.

Signed-off-by: Tamas Ban <t

feat(tc): group components into certificates

Set the cert_id argument to group the components
into certificates. The grouping reflects the likely units
of updateability.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ie7a1f10c84af727d0cd39e3a78b0cb59cbc2e457

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feat(tc): add dummy TRNG support to be able to boot pVMs

pVMs on Android 14 has a platform requirement to support
SMCCC TRNG discovery. This implementation add a
dummy TRNG support to TC2.

Signed-o

feat(tc): add dummy TRNG support to be able to boot pVMs

pVMs on Android 14 has a platform requirement to support
SMCCC TRNG discovery. This implementation add a
dummy TRNG support to TC2.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iae0ca546cadf48a6a404ae578c7ccf5a84d057c4

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feat(tc): get the parent component provided DPE context_handle

Each client who wants to communicate with the DPE service
must own a valid context handle issued by the DPE service.
A context handle c

feat(tc): get the parent component provided DPE context_handle

Each client who wants to communicate with the DPE service
must own a valid context handle issued by the DPE service.
A context handle can be used for a single time then it will
be invalidated by the DPE service. In case of calls from
the same component, the next valid context handle is
returned in the response to a DPE command. When a component
finishes their job then the next component in the boot flow
inherits its first context handle from its parent.
How the inheritance is done can be client or
platform-dependent. It can be shared through shared
memory or be part of a DTB object passed to the next
bootloader stage.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: Ic82f074f1c5b15953e78f9fa5404ed7f48674cbb

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feat(tc): share DPE context handle with child component

To be allowed to communicate with DPE service all
components must own a valid context handle. The first
valid context handle is inherited from

feat(tc): share DPE context handle with child component

To be allowed to communicate with DPE service all
components must own a valid context handle. The first
valid context handle is inherited from the parent
component via a DTB object.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id357fab3586398b1933444e1d10d1ab6d8243ab9

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feat(tc): add DPE context handle node to device tree

Child software components are inheriting their first valid
DPE context handle from their parent components (who loaded
and measured them). The co

feat(tc): add DPE context handle node to device tree

Child software components are inheriting their first valid
DPE context handle from their parent components (who loaded
and measured them). The context handle is shared through
the device tree object the following way:
- BL1 -> BL2 via TB_FW_CONFIG
- BL2 -> BL33 via NT_FW_CONFIG

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9bf7808fb13a310ad7ca1895674a0c7e6725e08b

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feat(tc): add DPE backend to the measured boot framework

The client platform relies on the DICE attestation
scheme. RSS provides the DICE Protection Environment
(DPE) service. TF-A measured boot fra

feat(tc): add DPE backend to the measured boot framework

The client platform relies on the DICE attestation
scheme. RSS provides the DICE Protection Environment
(DPE) service. TF-A measured boot framework supports
multiple backends. A given platform always enables
the corresponding backend which is required by the
attestation scheme.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Idc3360d0d7216e4859e99b5db3d377407e0aeee5

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refactor(tc): align image identifier string macros

Macros were renamed, align with new names.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id7a556da34381618577fed4039d9ca957754cd7c

refactor(arm): console runtime switch on bl31 exit

Any BL31 setup and Runtime initialization within BL31 is still part of
the BOOT process. As such, the console flush and switch must be the
last cal

refactor(arm): console runtime switch on bl31 exit

Any BL31 setup and Runtime initialization within BL31 is still part of
the BOOT process. As such, the console flush and switch must be the
last calls before BL31 exit. Flush the console print buffer before
switching to runtime. This is so that there is no lingering chars in
the print buffer when we move to the runtime console.

This patch adds console flush before switching to runtime in
bl31_plat_runtime_setup() function (before BL31 exits). The plan is to
move flush and switch calls to bl31_main before BL31 exits, until then
console_flush() in bl31_main.c has been left as is.

This patch affects the Arm platform only.

Change-Id: I4d367b9e9640686ac15246ad24318ae4685c12c5
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(tc): reorder config variable defines

They are very scattered, hard to read, and especially hard to track
down. As a result some are duplicate and some are overridden in the
downstream as it

refactor(tc): reorder config variable defines

They are very scattered, hard to read, and especially hard to track
down. As a result some are duplicate and some are overridden in the
downstream as it's simpler.

Put all variables at the top of the platform makefile. Also drop setting
variables that don't change from their default values
(CTX_INCLUDE_EL2_REGS, ARCH, ENABLE_FEAT_RAS, SDEI_SUPPORT,
EL3_EXCEPTION_HANDLING, HANDLE_EA_EL3_FIRST_NS, ENABLE_SPE_FOR_NS).

While we're at it, add some variables that are necessary. SPMD
requires MTE registers to be saved, BRANCH_PROTECTION, as well as
running at SEL2. All of our CPUs are Armv8.7 compliant so we can have
ARM_ARCH_MINOR=7 (and drop ENABLE_TRF_FOR_NS which it includes).

Finally, drop the override directives as there's no reason to prohibit
experimentation (even if incorrect).

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6ac596934952aab8abf5d4db5220e13a4941a10c

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refactor(tc): move DTB to start of DRAM

Now that tf-a passes the DTB address to BL33, its location doesn't
matter. Since we declare a fixed size for it (32K) put it at the start
of ram to not fragme

refactor(tc): move DTB to start of DRAM

Now that tf-a passes the DTB address to BL33, its location doesn't
matter. Since we declare a fixed size for it (32K) put it at the start
of ram to not fragment memory. This has the added benefit of
"supporting" larger kernel sizes which are breaking with the current
location.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib0e4e5cf780bd58a49a34d72085b0a0914c340ed

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refactor(tc): correlate secure world addresses with platform_def

Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manife

refactor(tc): correlate secure world addresses with platform_def

Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manifest and NS
related entries automatically. Use the macros directly so any changes
can propagate automatically.

The result of this is that TC3 and above get correct secure world
manifests automatically. They were previously broken.

One "breaking" change is that the FWU region moves. This should have
happened previously but it was missed when the secure portion of DRAM
was increased, leaving it in secure memory. This was caught when going
over the definitions and correlating them should prevent this in the
future.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1415e402be8c70f5e22f28eabddcb53298c57a11

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feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't com

feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.

By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326

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feat(tc): pass the DTB address to BL33 in R0

The DTB that tf-a loads is already used in BL33 directly with the
address hardcoded. As this address is prone to changing, pass it forward
so we can avoi

feat(tc): pass the DTB address to BL33 in R0

The DTB that tf-a loads is already used in BL33 directly with the
address hardcoded. As this address is prone to changing, pass it forward
so we can avoid breakage in the future.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7a42f72ecc00814b9f0a4bf5605d70cb53ce2ff4

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feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU

feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.

These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.

For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1

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feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The dif

feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)

Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.

Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.

Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13

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feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arran

feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).

Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.

While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.

Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.

In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b

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feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utili

feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different

This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827

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feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRA

feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRAM1 bank. If we want to access it it needs
to be mapped to memory.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I45e0fbb016e8f615d41b6ad9da0d1e7b466ece72

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feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total c

feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.

Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.

Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847

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