Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
f

Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2
feat(per-cpu): migrate amu_ctx to per-cpu framework
feat(per-cpu): migrate spm_core_context to per-cpu framework
feat(per-cpu): migrate psci_ns_context to per-cpu framework
feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework
feat(per-cpu): migrate rmm_context to per-cpu framework
feat(per-cpu): integrate per-cpu framework into BL31/BL32
feat(per-cpu): introduce framework accessors/definers
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
docs(changelog): add scope for per-cpu framework

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feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cp

feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cpu objects within a memory that is local to a particular node.
RD-V3-Cfg2 in this case has the per-cpu objects distributed across
different SRAMs present on the system.

introduce platform-specific helper functions to enhance the per_cpu
framework. Adds a helper function to zero init per_cpu sections,
ensuring clean initialization of per-cpu data. Introduces a function
to obtain the base address of per_cpu sections, facilitating efficient
access to per-CPU data structures. Enhances the per_cpu framework's
capability to handle platform-specific requirements.

These additions are crucial for maintaining the integrity and
performance of per-cpu operations.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I550c6b5c59f80fbe2b746a1261cda857f4fb1990

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Merge "fix(rdv3): correctly handle FP regs context saving" into integration

fix(rdv3): correctly handle FP regs context saving

Commit fe488c3796e01187fb6cffdd27a1bee1a33e0931 added an override to
force `CTX_INCLUDE_SVE_REGS` to 0 when `SPD == spmd` and
`SPMD_SPM_AT_SEL2 ==

fix(rdv3): correctly handle FP regs context saving

Commit fe488c3796e01187fb6cffdd27a1bee1a33e0931 added an override to
force `CTX_INCLUDE_SVE_REGS` to 0 when `SPD == spmd` and
`SPMD_SPM_AT_SEL2 == 1`.
Since there is an architectural dependency between FP and SVE registers,
`CTX_INCLUDE_FPREGS` must also be overridden to 0 when
CTX_INCLUDE_SVE_REGS is 0.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I1cd834241a2d5a5368ac532a348d8729a701bbcd

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Merge changes from topic "gr/build_fix_spmd" into integration

* changes:
fix(rdv3): handle invalid build combination
fix(build): handle invalid spd build options

fix(rdv3): handle invalid build combination

`CTX_INCLUDE_SVE_REGS` should not be enabled when building with
SPD=spmd and SPMD_SPM_AT_SEL2=1 both been used.

Unfortunately a check at top level makefi

fix(rdv3): handle invalid build combination

`CTX_INCLUDE_SVE_REGS` should not be enabled when building with
SPD=spmd and SPMD_SPM_AT_SEL2=1 both been used.

Unfortunately a check at top level makefile ignored this, now its been
fixed at top level makefile. Ensure correct combination are handled,
otherwise it will lead to build failures.

Change-Id: Ib84fc0096c92d9b3d56366c0e1d77b6d83098221
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes I712712d7,I1932500e,I75dda77e,I12f3b8a3,Ia72e5900 into integration

* changes:
refactor(rse)!: remove rse_comms_init
refactor(arm): switch to rse_mbx_init
refactor(rse): put MHU c

Merge changes I712712d7,I1932500e,I75dda77e,I12f3b8a3,Ia72e5900 into integration

* changes:
refactor(rse)!: remove rse_comms_init
refactor(arm): switch to rse_mbx_init
refactor(rse): put MHU code in a dedicated file
refactor(tc): add plat_rse_comms_init
refactor(arm)!: rename PLAT_MHU_VERSION flag

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refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, M

refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, MHUv1, MHUv2, MHUv3...

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia72e590088ce62ba8c9009f341b6135926947bee

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Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3

Merge changes from topic "RDV3-hafnium-support" into integration

* changes:
feat(rdv3): enable the support to fetch dynamic config
feat(rdv3): add dts files to enable hafnium as BL32
feat(rdv3): define SPMC manifest base address
feat(arm): add a macro for SPMC manifest base address
feat(rdv3): add carveout for BL32 image
feat(rdv3): introduce platform handler for Group0 interrupt
feat(neoverse-rd): use larger stack size when S-EL2 spmc is enabled
fix(neoverse-rd): set correct SVE vector lengths

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feat(rdv3): enable the support to fetch dynamic config

To enable the support to load Hafnium as BL32, BL31 needs firmware
configuration info to get BL32 manifest load location. The load address
of B

feat(rdv3): enable the support to fetch dynamic config

To enable the support to load Hafnium as BL32, BL31 needs firmware
configuration info to get BL32 manifest load location. The load address
of BL32 is passed via firmware config info.

Add the support to get the address using fconf framework from dynamic
config info.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I3a2a5706789ed290dc7f4a67e62e03751b930c02

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feat(rdv3): add dts files to enable hafnium as BL32

On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32

feat(rdv3): add dts files to enable hafnium as BL32

On RD-V3 platform and variants, Hafnium is used as SPMC running at
S-EL2 and manage SP running at S-EL0. Hafnium is loaded and configured
as BL32 image. SP is loaded by SP load framework and configured by
Hafnium.

Add the dts files needed to enable load and configuration of hafnium and
SP.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I7de72052323ff9106d7bedbaaf5ece3272e9a6cd

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fix(neoverse-rd): set correct SVE vector lengths

Affected platforms: RD-N2, RD-V1, RD-V1-MC, RD-V3 and their
configurations.

Previously, the SVE vector lengths for these platforms were
being taken

fix(neoverse-rd): set correct SVE vector lengths

Affected platforms: RD-N2, RD-V1, RD-V1-MC, RD-V3 and their
configurations.

Previously, the SVE vector lengths for these platforms were
being taken from the default configuration. This commit updates
their respective platform.mk files to specify the correct vector
lengths.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8919257e2cec5c0e819424ff44a623dc3ab1a368

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Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow
feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3
feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

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feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@a

feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8947660bb96fdf2f178e560b387e4bc93bf68abf

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Merge "feat(rdv3): set CTX_INCLUDE_SVE_REGS build flag for RD-V3 variants" into integration

feat(rdv3): set CTX_INCLUDE_SVE_REGS build flag for RD-V3 variants

Commit 4242262(feat(simd):add sve state to simd ctxt struct)
introduced the CTX_INCLUDE_SVE_REGS build flag that needs to be set
if

feat(rdv3): set CTX_INCLUDE_SVE_REGS build flag for RD-V3 variants

Commit 4242262(feat(simd):add sve state to simd ctxt struct)
introduced the CTX_INCLUDE_SVE_REGS build flag that needs to be set
if SVE is enabled for more than one world, which is the case for
RD-V3. This build flag enables SVE registers to be included when
saving and restoring the CPU context.

Change-Id: Ic491939061e42e8c87a805ded99e271308f90352
Signed-off-by: Gautham Ravichandran <gautham.ravichandran@arm.com>

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Merge "fix(rdv3): remove NEED_* from RD-V3 makefile" into integration

fix(rdv3): remove NEED_* from RD-V3 makefile

As the NEED_* are internal flags used in the build system and are not
meant to be used by platforms, remove them from the RD-V3 makefile.

Signed-off-by:

fix(rdv3): remove NEED_* from RD-V3 makefile

As the NEED_* are internal flags used in the build system and are not
meant to be used by platforms, remove them from the RD-V3 makefile.

Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com>
Change-Id: If7144b9d72c16e8025f929f2546abd96194615ce

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Merge "chore(rdv3): rename platform RD-Fremont to RD-V3" into integration

chore(rdv3): rename platform RD-Fremont to RD-V3

Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurenc

chore(rdv3): rename platform RD-Fremont to RD-V3

Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurences of "Fremont" with "V3" in file names and
contents.

Change-Id: I302103492f962a7ac74854633ad68701b2a7f420
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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