1# Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6RD_V3_VARIANTS := 0 1 2 7ifneq ($(NRD_PLATFORM_VARIANT), \ 8 $(filter $(NRD_PLATFORM_VARIANT),$(RD_V3_VARIANTS))) 9 $(error "NRD_PLATFORM_VARIANT for RD-V3 should be 0, 1, or 2," 10 "currently set to ${NRD_PLATFORM_VARIANT}.") 11endif 12 13$(eval $(call CREATE_SEQ,SEQ,4)) 14ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ))) 15 $(error "Chip count for RD-V3-MC should be either $(SEQ) \ 16 currently it is set to ${NRD_CHIP_COUNT}.") 17endif 18 19# Build options 20# Major and Minor versions 21override ARM_ARCH_MAJOR := 8 22override ARM_ARCH_MINOR := 7 23 24# Misc options 25override CTX_INCLUDE_AARCH32_REGS := 0 26 27ifeq (${PLAT_RESET_TO_BL31}, 1) 28# Support for BL31 boot flow 29override RESET_TO_BL31 := 1 30 31# arm_common.mk sets ENABLE_PIE=1, but Makefile blocks PIE for RME 32override ENABLE_PIE := 0 33 34# Non Trusted Firmware parameters 35override ARM_PRELOADED_DTB_BASE := 0xF3000000 36override ARM_LINUX_KERNEL_AS_BL33 := 1 37override PRELOADED_BL33_BASE := 0xE0000000 38 39# These are internal build flags but as of now RESET_TO_BL31 won't work without defining them 40override NEED_BL1 := no 41override NEED_BL2 := no 42override NEED_BL32 := no 43endif 44 45# RD-V3 platform uses GIC-700 which is based on GICv4.1 46GIC_ENABLE_V4_EXTN := 1 47 48# Enable GIC multichip extension only for multichip platforms 49ifeq (${NRD_PLATFORM_VARIANT}, 2) 50GICV3_IMPL_GIC600_MULTICHIP := 1 51endif 52 53# RD-V3 uses MHUv3 54PLAT_MHU := MHUv3 55 56ifeq (${NRD_PLATFORM_VARIANT}, 2) 57override PLATFORM_NODE_COUNT := NRD_CHIP_COUNT 58endif 59 60include plat/arm/board/neoverse_rd/common/nrd-common.mk 61include drivers/arm/rse/rse_comms.mk 62include drivers/auth/mbedtls/mbedtls_common.mk 63ifeq (${MEASURED_BOOT},1) 64include drivers/measured_boot/rse/rse_measured_boot.mk 65endif 66 67RDV3_BASE = plat/arm/board/neoverse_rd/platform/rdv3 68 69PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd3/ \ 70 -I${RDV3_BASE}/include/ \ 71 -Iinclude/lib/psa 72 73NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S 74 75# Source files for RD-V3 variants 76PLAT_BL_COMMON_SOURCES \ 77 += ${NRD_COMMON_BASE}/nrd_plat3.c \ 78 ${RDV3_BASE}/rdv3_common.c 79 80PLAT_MEASURED_BOOT_SOURCES \ 81 := ${MEASURED_BOOT_SOURCES} \ 82 ${RSE_COMMS_SOURCES} \ 83 ${RDV3_BASE}/rdv3_common_measured_boot.c \ 84 lib/psa/measured_boot.c 85 86BL1_SOURCES += ${NRD_CPU_SOURCES} \ 87 ${RDV3_BASE}/rdv3_err.c \ 88 ${RDV3_BASE}/rdv3_mhuv3.c 89ifeq (${TRUSTED_BOARD_BOOT}, 1) 90BL1_SOURCES += ${RDV3_BASE}/rdv3_trusted_boot.c 91endif 92ifeq (${MEASURED_BOOT},1) 93BL1_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \ 94 ${RDV3_BASE}/rdv3_bl1_measured_boot.c 95endif 96 97BL2_SOURCES += ${RDV3_BASE}/rdv3_bl2_setup.c \ 98 ${RDV3_BASE}/rdv3_err.c \ 99 ${RDV3_BASE}/rdv3_mhuv3.c \ 100 ${RDV3_BASE}/rdv3_security.c \ 101 lib/utils/mem_region.c \ 102 plat/arm/common/arm_nor_psci_mem_protect.c 103ifeq (${TRUSTED_BOARD_BOOT}, 1) 104BL2_SOURCES += ${RDV3_BASE}/rdv3_trusted_boot.c 105endif 106ifeq (${MEASURED_BOOT},1) 107BL2_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \ 108 ${RDV3_BASE}/rdv3_bl2_measured_boot.c 109endif 110 111ifeq (${PLAT_RESET_TO_BL31}, 1) 112BL31_SOURCES += ${RDV3_BASE}/rdv3_security.c 113endif 114 115BL31_SOURCES += ${NRD_CPU_SOURCES} \ 116 ${MBEDTLS_SOURCES} \ 117 ${RSE_COMMS_SOURCES} \ 118 ${RDV3_BASE}/rdv3_bl31_setup.c \ 119 ${RDV3_BASE}/rdv3_mhuv3.c \ 120 ${RDV3_BASE}/rdv3_topology.c \ 121 ${RDV3_BASE}/rdv3_plat_attest_token.c \ 122 ${RDV3_BASE}/rdv3_realm_attest_key.c \ 123 drivers/arm/smmu/smmu_v3.c \ 124 drivers/cfi/v2m/v2m_flash.c \ 125 lib/psa/cca_attestation.c \ 126 lib/psa/delegated_attestation.c \ 127 lib/utils/mem_region.c \ 128 plat/arm/common/arm_dyn_cfg.c \ 129 plat/arm/common/arm_nor_psci_mem_protect.c 130ifeq (${NRD_PLATFORM_VARIANT}, 2) 131BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c 132endif 133 134ifneq ($(filter-out 0 1,$(strip $(PLATFORM_NODE_COUNT))),) 135BL31_SOURCES += ${RDV3_BASE}/rdv3_per_cpu.S 136endif 137 138ifneq (${PLAT_RESET_TO_BL31}, 1) 139ifeq ($(SPMD_SPM_AT_SEL2),1) 140# Firmware Configuration Framework sources 141BL31_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES} 142endif 143endif 144 145# XLAT options for RD-V3 variants 146BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 147BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 148 149# Add the FDT_SOURCES and options for Dynamic Config 150FDT_SOURCES += ${RDV3_BASE}/fdts/${PLAT}_fw_config.dts \ 151 ${RDV3_BASE}/fdts/${PLAT}_tb_fw_config.dts \ 152 ${RDV3_BASE}/fdts/${PLAT}_nt_fw_config.dts 153 154ifeq (${SPMD_SPM_AT_SEL2}, 1) 155BL32_CONFIG_DTS := ${RDV3_BASE}/fdts/${PLAT}_spmc_sp_manifest.dts 156FDT_SOURCES += ${BL32_CONFIG_DTS} 157TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${BL32_CONFIG_DTS})).dtb 158endif 159 160FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 161TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 162NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 163 164# Add the FW_CONFIG to FIP and specify the same to certtool 165$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 166# Add the TB_FW_CONFIG to FIP and specify the same to certtool 167$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 168# Add the NT_FW_CONFIG to FIP and specify the same to certtool 169$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config)) 170 171# Features for RD-V3 variants 172override ENABLE_FEAT_MPAM := 2 173override ENABLE_FEAT_AMU := 2 174override ENABLE_SVE_FOR_SWD := 1 175override ENABLE_SVE_FOR_NS := 2 176override ENABLE_FEAT_MTE2 := 2 177 178# FEAT_SVE related flags 179override SVE_VECTOR_LEN := 128 180 181override CTX_INCLUDE_SVE_REGS := 1 182 183# Enabling CTX_INCLUDE_SVE_REGS along with SPMD_SPM_AT_SEL2=1 is a invalid 184# combination and will lead to build failure, use them only when SPMD_SPM_AT_SEL2=0 185# In this combination its SPMC responsbility to save SVE regs. 186ifeq (${SPD},spmd) 187ifeq (${SPMD_SPM_AT_SEL2},1) 188override CTX_INCLUDE_SVE_REGS := 0 189override CTX_INCLUDE_FPREGS := 0 190endif 191endif 192