Merge "refactor(arm/common): gate coherency behind flag" into integration

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refacto

Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refactor(gic): promote most of the GIC driver to common code
refactor: make arm_gicv2.c and arm_gicv3.c common
refactor(fvp): use more arm generic code for gicv3

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refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is

refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is difficult as their use is platform specific. So copy them to a
generic place and redirect platforms to them.

The new copies will remain for compatibility for platforms that don't
want to or can't take up upcoming refactors and the old copies can be
drastically refactored to make them more widely applicable.

Change-Id: I056c8710cdda4d8a81b324d392762c29e02cdae1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "gr/build_refactor" into integration

* changes:
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arc

Merge changes from topic "gr/build_refactor" into integration

* changes:
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arch features handling
build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR
refactor(build): reorder platform Makefile evaluation

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build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR

n1sdp based out of Arm Neoverse N1 Core uses Arm®v8.2‑A extensions
so set ARM_ARCH_MAJOR.ARM_ARCH_MINOR for n1sdp platform to 8.2

Change-Id: Ib70c6be

build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR

n1sdp based out of Arm Neoverse N1 Core uses Arm®v8.2‑A extensions
so set ARM_ARCH_MAJOR.ARM_ARCH_MINOR for n1sdp platform to 8.2

Change-Id: Ib70c6be5e12817961430870d50fb1b0efca32df2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(n1sdp): add platform-specific power domain functions" into integration

fix(n1sdp): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turn

fix(n1sdp): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turning off both cores in a cluster would cause a hang when powering
back on either core. This change introduced issues on other platforms
with a different GIC implementation, and was reverted in commit
60719e4e0965aead49d927f12bf2a37bd2629012.

This commit uses the previous fix in platform-specific implementations
of power domain off/suspend functions.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I52c463646c494fe931ff4ce47afb940a56978fcd

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Merge "(feat)n1sdp: add support for OP-TEE SPMC" into integration

(feat)n1sdp: add support for OP-TEE SPMC

These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.

Signed-off-by: Vishnu Banavath <vishnu.banavath@

(feat)n1sdp: add support for OP-TEE SPMC

These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.

Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I0514db646d4868b6f0c56f1ea60495cb3f7364fd

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Merge changes I2fcf13b7,I153ccb43 into integration

* changes:
feat(n1sdp): add support for nt_fw_config
feat(n1sdp): enable trusted board boot on n1sdp

feat(n1sdp): add support for nt_fw_config

This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil

feat(n1sdp): add support for nt_fw_config

This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a

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feat(n1sdp): enable trusted board boot on n1sdp

Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e

Merge "Add support for Neoverse-N2 CPUs." into integration

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8

Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad

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Merge "fdts: n1sdp: DTS file for single-chip and multi-chip environment." into integration

fdts: n1sdp: DTS file for single-chip and multi-chip environment.

N1SDP supports both single-chip and multi-chip environment.
Added DTS file for both type of environment.
Enabled DTS files compilat

fdts: n1sdp: DTS file for single-chip and multi-chip environment.

N1SDP supports both single-chip and multi-chip environment.
Added DTS file for both type of environment.
Enabled DTS files compilation for N1SDP platform.

Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0
Co-authored-by: Robin Murphy <Robin.Murphy@arm.com>
Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com>
Co-authored-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>

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Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration

GICv3: GIC-600: Detect GIC-600 at runtime

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at r

GICv3: GIC-600: Detect GIC-600 at runtime

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "TF-A GICv3 driver: Introduce makefile" into integration

TF-A GICv3 driver: Introduce makefile

This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affectin

TF-A GICv3 driver: Introduce makefile

This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.

NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.

Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag" into integration

Merge "TF-A GICv3 driver: Separate GICD and GICR accessor functions" into integration

n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag

Since N1SDP has a system level cache which is an
external LLC enable the NEOVERSE_N1_EXTERNAL_LLC flag.

Change-Id: Idb34274e61e7fd9db5485862a0caa497f

n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag

Since N1SDP has a system level cache which is an
external LLC enable the NEOVERSE_N1_EXTERNAL_LLC flag.

Change-Id: Idb34274e61e7fd9db5485862a0caa497f3e290c7
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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