feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the p

feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the primary and
gate secondary core startup inline to existing implementation for
secondary cores.

Change-Id: I6a5d76f23d4d4c4139d95bbaf55edf1244f2dbfe
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from

fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from plat_my_core_pos() results in the return address stored in register
x30 becoming invalid and register x9 (used later) ends up with the value
0x0. Consequently, the CPU branches to address 0x0, triggering a
synchronous exception. TF-A then invokes the BHB flush code before
resuming execution. However, since the stack is not properly initialized
at this stage, the system eventually enters plat_panic_handler().
In the updated implementation, the platform_get_core_pos() function
is redefined in assembly to provide tighter control during early boot
stages. The MPIDR_EL1 register contains three affinity levels: Aff0
(bits [0:7]), Aff1 (bits [8:15]), and Aff2 (bits [16:23]). In this
assembly function, the core ID is extracted from Aff1
(MPIDR_AFF1_SHIFT), and the cluster ID from Aff2 (MPIDR_AFF2_SHIFT).
cluster/core ID calculation. The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: Id532bbcd68f18e87ceba01c8f961d8c15962a1a3
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer fre

fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer frequency and cpu idle with cpu power down state is not
working. So update CNTFRQ_EL0 value during initialization.

Change-Id: I238f67521bbc338c433ce18f60df51efc4c5f387
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq,

fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq, which is
incorrect. Use the common plat_get_syscnt_freq2() to read the IOU_SCNTR
frequency register and return the correct value.

Change-Id: I277dc6a2e4acd1acd3f048aaf242a3580d06e1c8
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consist

fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consistency across platforms and enables the use of a common
function for getting and setting the system counter-timer
frequency.

Change-Id: I257a1086d77350858d63859b0fbe6e2b47deb9e5
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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feat(versal2): update platform version to versal2

Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and

feat(versal2): update platform version to versal2

Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and version
information is also printed for chip identification.

Change-Id: Ia37418f6a31426a5763fb89fc76fef91d09df155
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(versal2): typecast expressions to match data type

This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have th

fix(versal2): typecast expressions to match data type

This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): variable conflicting with external linkage

This corrects the MISRA violation C2012-5.8:
Identifiers that define objects or functions with
external linkage shall be unique.
Modify the v

fix(versal2): variable conflicting with external linkage

This corrects the MISRA violation C2012-5.8:
Identifiers that define objects or functions with
external linkage shall be unique.
Modify the variable name to prevent conflict with
external object linkage.

Change-Id: I2448e4ad0660e654ceb40940e0046d2f2899b41b
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): update check for TRANSFER_LIST macro

Replace #if defined(TRANSFER_LIST) by #if TRANSFER_LIST.
By default TRANSFER_LIST macro is defined with value 0 in Makefile.
So checking if the mac

fix(versal2): update check for TRANSFER_LIST macro

Replace #if defined(TRANSFER_LIST) by #if TRANSFER_LIST.
By default TRANSFER_LIST macro is defined with value 0 in Makefile.
So checking if the macro is defined will always be true and instead
need to check the value of the macro to add the conditional code.

Change-Id: I90b06f378326d5e03ad576377ad173e81b100f56
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

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