refactor(plat/allwinner): clean up platform definitions

Group the SCP base/size definitions in a more logical location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d8

refactor(plat/allwinner): clean up platform definitions

Group the SCP base/size definitions in a more logical location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d855a2413173d674a5ee666527808

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refactor(plat/allwinner): do not map BL32 DRAM at EL3

BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.

Signed-off-by: Samuel Holland <samuel@sho

refactor(plat/allwinner): do not map BL32 DRAM at EL3

BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74

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refactor(plat/allwinner): map SRAM as device memory by default

The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by defaul

refactor(plat/allwinner): map SRAM as device memory by default

The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by default.
This scheme requires carveouts and cache maintenance code for proper
synchronization with the coprocessor.

A better scheme is to only map pages owned by BL31 as normal memory,
and leave everything else as device memory. This removes the need for
cache maintenance, and it makes the mapping for BL31 RW data explicit
instead of magic.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348

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refactor(plat/allwinner): rename static mmap region constant

This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.

Signed-off-by: Samuel Holland <sam

refactor(plat/allwinner): rename static mmap region constant

This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36

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allwinner: H616: Add reserved-memory node to DT

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-

allwinner: H616: Add reserved-memory node to DT

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.

Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Add Allwinner H616 SoC support

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DR

allwinner: Add Allwinner H616 SoC support

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Add H616 SoC ID

Change-Id: I557fd05401e24204952135cf3ca26479a43ad1f1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

allwinner: Express memmap more dynamically

In preparation for changing the memory map, express the locations of the
various code and data pieces more dynamically, allowing SoCs to override
the memma

allwinner: Express memmap more dynamically

In preparation for changing the memory map, express the locations of the
various code and data pieces more dynamically, allowing SoCs to override
the memmap later.
Also prepare for the SCP region to become optional.

No functional change.

Change-Id: I7ac01e309be2f23bde2ac2050d8d5b5e3d6efea2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Move sunxi_cpu_power_off_self() into platforms

The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new pl

allwinner: Move sunxi_cpu_power_off_self() into platforms

The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new platforms easier, move sunxi_cpu_power_off_self()
into the SoC directory, so we don't need to carry definitions for both
methods for all SoCs.

On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
of all the code to program the ARISC, which is now only needed for the
A64 version.

Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Move SEPARATE_NOBITS_REGION to platforms

For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move
some parts of the data into separate memory regions (to save on the SRAM

allwinner: Move SEPARATE_NOBITS_REGION to platforms

For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move
some parts of the data into separate memory regions (to save on the SRAM
A2 we are loaded into).
For the upcoming H616 platform this is of no concern (we run in DRAM),
so make this flag a platform choice instead.

Change-Id: Ic01d49578c6274660f8f112bd23680d3eca3be7a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Use CPUIDLE hardware when available

This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de7

allwinner: Use CPUIDLE hardware when available

This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Allow conditional compilation of SCPI and native PSCI ops

Now that we have split the native and the SCPI version of the PSCI ops,
we can introduce build options to compile in either or bo

allwinner: Allow conditional compilation of SCPI and native PSCI ops

Now that we have split the native and the SCPI version of the PSCI ops,
we can introduce build options to compile in either or both of them.

If one version is not compiled in, some stub functions make sure the
common code still compiles and makes the right decisions.

By default both version are enabled (as before), but one of them can be
disabled on the make command line, or via a platform specific Makefile.

Change-Id: I0c019d8700c0208365eacf57809fb8bc608eb9c0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: Split native and SCPI-based PSCI implementations

In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out

allwinner: Split native and SCPI-based PSCI implementations

In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out to be
a good decision, as some newer SoCs omit the ARISC, and thus cannot run
SCP firmware.

However, keeping the two implementations in one file makes things
unnecessarily messy. First, it is difficult to compile out the
SCPI-based implementation where it is not applicable. Second the check
is done in each callback, while scpi_available is only updated at boot.
This makes the individual callbacks unnecessarily complicated.

It is cleaner to provide two entirely separate implementations in two
separate files. The native implementation does not support any kind of
CPU suspend, so its callbacks are greatly simplified. One function,
sunxi_validate_ns_entrypoint, is shared between the two implementations.

Finally, the logic for choosing between implementations is kept in a
third file, to provide for platforms where only one implementation is
applicable and the other is compiled out.

Change-Id: I4914f07d8e693dbce218e0e2394bef15c42945f8
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: psci: Improve system shutdown/reset sequence

- When the SCPI shutdown/reset command returns success, the SCP is
still waiting for the CPU to enter WFI. Do that.
- Peform board-level pow

allwinner: psci: Improve system shutdown/reset sequence

- When the SCPI shutdown/reset command returns success, the SCP is
still waiting for the CPU to enter WFI. Do that.
- Peform board-level poweroff before CPU poweroff. If there is a PMIC
available, it will turn everything off including the CPUs, so doing
CPU poweroff first is a waste of cycles.
- During poweroff, attempt to turn off the local CPU using the ARISC.
This should use slightly less power than just an infinite WFI.
- Drop the WFI in the reset failure path. The panic will hang anyway.

Change-Id: I897efecb3fe4e77a56041b97dd273156ec51ef8e
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback

When operating on the local cpu, sunxi_cpu_power_off_self() only "arms"
the ARISC to perform the power-off process; the SCP waits for the CPU

allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback

When operating on the local cpu, sunxi_cpu_power_off_self() only "arms"
the ARISC to perform the power-off process; the SCP waits for the CPU to
enter WFI before acutally powering it off. Since this matches the
expected split between .pwr_domain_off and .pwr_domain_pwr_down_wfi, we
can move the sunxi_cpu_power_off_self() call to sunxi_pwr_domain_off().
Since that change makes sunxi_pwr_down_wfi() equivalent to the default
implementation, the callback is no longer needed.

Change-Id: I7d65f66c550d1c69fa5e9945affd7a25b3d3ef42
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: Separate code to power off self and other CPUs

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.

allwinner: Separate code to power off self and other CPUs

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.
This actually simplifies things, because all callers either operate on
the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
(sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
to choose the appropriate code path.

Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: Leave CPU power alone during BL31 setup

Disabling secondary CPUs during boot is unnecessary because the other
CPUs are already in reset, and it saves an entirely insignificant amount
of p

allwinner: Leave CPU power alone during BL31 setup

Disabling secondary CPUs during boot is unnecessary because the other
CPUs are already in reset, and it saves an entirely insignificant amount
of power. Let's remove this bit of code that was added mostly "because
we can", and along with it remove an unconditional dependency on the CPU
ops functions.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7

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allwinner: psci: Invert check in .validate_ns_entrypoint

Checking the exceptional case and letting the success case fall through
is not only more idiomatic, but it also allows adding more exceptiona

allwinner: psci: Invert check in .validate_ns_entrypoint

Checking the exceptional case and letting the success case fall through
is not only more idiomatic, but it also allows adding more exceptional
cases in the future, such as a check for overlapping secure DRAM.

Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: psci: Drop MPIDR check from .pwr_domain_on

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b

allwinner: psci: Drop MPIDR check from .pwr_domain_on

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: psci: Drop .get_node_hw_state callback

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary

allwinner: psci: Drop .get_node_hw_state callback

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary contract. First, the SCPI protocol has no way to represent
HW_STANDBY at the CPU power level. Second, the SCPI implementation
maintains its own logical view of power states, and its implementation
of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
Thus it cannot provide "the physical view of power state", as required
for this function by the PSCI specification.

Since the function is optional, drop it.

Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
Signed-off-by: Samuel Holland <samuel@sholland.org>

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Merge changes I3703868b,Ie77476db into integration

* changes:
allwinner: Add SPC security setup for H6
allwinner: Add R_PRCM security setup for H6

Merge "allwinner: Fix non-default PRELOADED_BL33_BASE" into integration

Merge "allwinner: Enable workaround for Cortex-A53 erratum 1530924" into integration

allwinner: Use RSB for the PMIC connection on H6

RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
eithe

allwinner: Use RSB for the PMIC connection on H6

RSB is faster and more efficient, and it has a simpler driver. As long
as the PMIC is returned to I2C mode after use, the rich OS can later use
either bus.

Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: Enable workaround for Cortex-A53 erratum 1530924

BL31 reports the following warning during boot:

WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!

Resolve this by ena

allwinner: Enable workaround for Cortex-A53 erratum 1530924

BL31 reports the following warning during boot:

WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!

Resolve this by enabling the workaround on the affected platforms.

Change-Id: Ia1d5075370be5ae67b7bece96ec0069d9692b14c
Signed-off-by: Samuel Holland <samuel@sholland.org>

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