| 018c1d87 | 27-Mar-2023 |
Mikhail Kalashnikov <iuncuim@gmail.com> |
feat(allwinner): add support for Allwinner T507 SoC
The Allwinner T507 SoC is using the same die as the H616, but in a different package. On top of this, there is at least one different die revision
feat(allwinner): add support for Allwinner T507 SoC
The Allwinner T507 SoC is using the same die as the H616, but in a different package. On top of this, there is at least one different die revision out there, which uses a different CPU cluster control block. The same die revision has been spotted in some, but not all, H313 SoCs.
Apart from that IP block, the rest of the SoC seems the same, so we can support them using the existing H616 port. The die revision can be auto-detected, so there is no extra build option or knowledge needed.
Provide the deviating CPU power up/down sequence for the die variant. The new IP block uses per-core instead of per-cluster registers, but follows the same pattern otherwise.
Since the CPU ops code is shared among all Allwinner SoCs, we need to dummy-define the new register names for the older SoCs. The actual new code is guarded by a predicate function, that is hard coded to return true on the other SoCs. Since this is a static inline function in a header file, the compiler will optimise away the unneeded branch there, so the generated code for the other SoCs stays the same.
Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| fbde260b | 03-Apr-2023 |
Andre Przywara <andre.przywara@arm.com> |
feat(allwinner): add function to detect H616 die variant
Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, tha
feat(allwinner): add function to detect H616 die variant
Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, that differs in the way the CPU cores' power and reset controls are handled. This die variation can be detected by reading the SRAM version register.
Provide a predicate function that returns false if that die variant is used. Since the CPU power control code is shared for all supported SoCs, we provide an instance of this function for each SoC, as a static inline, and return true on all other SoCs. This allows to always use this function, and still let the compiler optimise away the unneeded branch for those older SoCs.
This function is unused for now, but is needed in the next patch.
Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| b15e2cda | 09-Dec-2022 |
Mikhail Kalashnikov <iuncuim@gmail.com> |
feat(allwinner): add extra CPU control registers
The die used in several variants of the Allwinner H616 SoC (H313, T507) seems to produced in at least two revisions. The newer one differs from the o
feat(allwinner): add extra CPU control registers
The die used in several variants of the Allwinner H616 SoC (H313, T507) seems to produced in at least two revisions. The newer one differs from the original by using a different CPU control register IP block.
Add those newly used register offsets to the respective header file. The MMIO block itself is actually present in both variants, though the registers are different. The new registers tend to use one register per core, in contrast to one register per cluster in the older revisions.
Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602 Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| e2b18771 | 23-Jan-2022 |
Samuel Holland <samuel@sholland.org> |
feat(allwinner): provide CPU idle states to the rich OS
When using SCPI as the PSCI backend, firmware can wake up the CPUs and cluster from sleep, so CPU idle states are available for the rich OS to
feat(allwinner): provide CPU idle states to the rich OS
When using SCPI as the PSCI backend, firmware can wake up the CPUs and cluster from sleep, so CPU idle states are available for the rich OS to use. In that case, advertise them to the rich OS via the DTB.
Change-Id: I718ef6ef41212fe5213b11b4799613adbbe6e0eb Signed-off-by: Samuel Holland <samuel@sholland.org>
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| 52466ec3 | 19-Mar-2021 |
Samuel Holland <samuel@sholland.org> |
feat(allwinner): simplify CPU_SUSPEND power state encoding
Use the encoding recommended by the PSCI specification: four bits for the power state at each power level.
SCPI provides no way to handsha
feat(allwinner): simplify CPU_SUSPEND power state encoding
Use the encoding recommended by the PSCI specification: four bits for the power state at each power level.
SCPI provides no way to handshake an exit from a standby state, so the only possible standby state is the architectural WFI state. Since WFI can be used outside of PSCI, we do not allow passing in standby states.
Change-Id: I4b3b84e5c255ee58a25255a0cab5d7623425086e Signed-off-by: Samuel Holland <samuel@sholland.org>
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| 159c36fd | 19-Mar-2021 |
Samuel Holland <samuel@sholland.org> |
feat(allwinner): choose PSCI states to avoid translation
Aligning the PSCI and SCPI power states avoids some code to translate between the two. This also makes room for an intermediate power state,
feat(allwinner): choose PSCI states to avoid translation
Aligning the PSCI and SCPI power states avoids some code to translate between the two. This also makes room for an intermediate power state, for future firmware capability growth.
Change-Id: I26691085f277a96bd405e3305ab0fe390a92b418 Signed-off-by: Samuel Holland <samuel@sholland.org>
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| 79808f10 | 23-Jan-2022 |
Samuel Holland <samuel@sholland.org> |
fix(allwinner): improve DTB patching error handling
Currently, if any step of the DTB patching process fails, the whole process is aborted. However, this causes some problems: - If any step modifie
fix(allwinner): improve DTB patching error handling
Currently, if any step of the DTB patching process fails, the whole process is aborted. However, this causes some problems: - If any step modifies the DTB (including fdt_open_into), the dcache must still be cleaned, even if some later step fails. - The DTB may need changes in multiple places; if one patch fails (for example due to missing nodes), we should still apply other patches. - Similarly, if some patch fails, we should still run fdt_pack to clean up after ourselves.
Change-Id: If1af2e58e5a7edaf542354bb8a261dd1c3da1ad0 Signed-off-by: Samuel Holland <samuel@sholland.org>
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| 3ccccc65 | 23-Jan-2022 |
Samuel Holland <samuel@sholland.org> |
refactor(allwinner): patch the DTB after setting up PSCI
Idle states are advertised to the rich OS by declaring them in the DTB. Since the availability of idle states depends on which PSCI implement
refactor(allwinner): patch the DTB after setting up PSCI
Idle states are advertised to the rich OS by declaring them in the DTB. Since the availability of idle states depends on which PSCI implementation was chosen, the DTB must be updated after PSCI setup.
Move this operation to bl31_plat_runtime_setup, the platform hook which happens at the right time. Defining this hook overrides the weak definition from plat/common, so copy over the code from there, too.
Change-Id: I42a83edb9cb28e1803d17dc2d73dbc879d885222 Signed-off-by: Samuel Holland <samuel@sholland.org>
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| 080939f9 | 22-Jul-2021 |
Icenowy Zheng <icenowy@sipeed.com> |
refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register called "General Control Register0" in the manual rather than the "Clus
refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register called "General Control Register0" in the manual rather than the "Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few macros instead assumed to be at bit offset 24 of SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668 Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
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