1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/css/css_scpi.h> 14 #include <drivers/arm/gicv2.h> 15 #include <drivers/delay_timer.h> 16 #include <lib/mmio.h> 17 #include <lib/psci/psci.h> 18 #include <plat/common/platform.h> 19 20 #include <sunxi_cpucfg.h> 21 #include <sunxi_def.h> 22 #include <sunxi_mmap.h> 23 #include <sunxi_private.h> 24 25 #define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010) 26 #define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014) 27 #define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018) 28 29 #define CPU_PWR_LVL MPIDR_AFFLVL0 30 #define CLUSTER_PWR_LVL MPIDR_AFFLVL1 31 #define SYSTEM_PWR_LVL MPIDR_AFFLVL2 32 33 #define CPU_PWR_STATE(state) \ 34 ((state)->pwr_domain_state[CPU_PWR_LVL]) 35 #define CLUSTER_PWR_STATE(state) \ 36 ((state)->pwr_domain_state[CLUSTER_PWR_LVL]) 37 #define SYSTEM_PWR_STATE(state) \ 38 ((state)->pwr_domain_state[SYSTEM_PWR_LVL]) 39 40 /* 41 * The addresses for the SCP exception vectors are defined in the or1k 42 * architecture specification. 43 */ 44 #define OR1K_VEC_FIRST 0x01 45 #define OR1K_VEC_LAST 0x0e 46 #define OR1K_VEC_ADDR(n) (0x100 * (n)) 47 48 /* 49 * This magic value is the little-endian representation of the or1k 50 * instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the 51 * first instruction in the SCP firmware. 52 */ 53 #define SCP_FIRMWARE_MAGIC 0xb4400012 54 55 static bool scpi_available; 56 57 static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state) 58 { 59 if (is_local_state_run(psci_state)) 60 return scpi_power_on; 61 if (is_local_state_retn(psci_state)) 62 return scpi_power_retention; 63 return scpi_power_off; 64 } 65 66 static void sunxi_cpu_standby(plat_local_state_t cpu_state) 67 { 68 u_register_t scr = read_scr_el3(); 69 70 assert(is_local_state_retn(cpu_state)); 71 72 write_scr_el3(scr | SCR_IRQ_BIT); 73 wfi(); 74 write_scr_el3(scr); 75 } 76 77 static int sunxi_pwr_domain_on(u_register_t mpidr) 78 { 79 if (scpi_available) { 80 scpi_set_css_power_state(mpidr, 81 scpi_power_on, 82 scpi_power_on, 83 scpi_power_on); 84 } else { 85 sunxi_cpu_on(mpidr); 86 } 87 88 return PSCI_E_SUCCESS; 89 } 90 91 static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) 92 { 93 plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state); 94 plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state); 95 plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state); 96 97 if (is_local_state_off(cpu_pwr_state)) 98 gicv2_cpuif_disable(); 99 100 if (scpi_available) { 101 scpi_set_css_power_state(read_mpidr(), 102 scpi_map_state(cpu_pwr_state), 103 scpi_map_state(cluster_pwr_state), 104 scpi_map_state(system_pwr_state)); 105 } else { 106 sunxi_cpu_power_off_self(); 107 } 108 } 109 110 static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) 111 { 112 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) 113 gicv2_distif_init(); 114 if (is_local_state_off(CPU_PWR_STATE(target_state))) { 115 gicv2_pcpu_distif_init(); 116 gicv2_cpuif_enable(); 117 } 118 } 119 120 static void __dead2 sunxi_system_off(void) 121 { 122 gicv2_cpuif_disable(); 123 124 if (scpi_available) { 125 /* Send the power down request to the SCP */ 126 uint32_t ret = scpi_sys_power_state(scpi_system_shutdown); 127 128 if (ret == SCP_OK) { 129 wfi(); 130 } 131 132 ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret); 133 } 134 135 /* Attempt to power down the board (may not return) */ 136 sunxi_power_down(); 137 138 /* Turn off all CPUs */ 139 sunxi_cpu_power_off_others(); 140 sunxi_cpu_power_off_self(); 141 psci_power_down_wfi(); 142 } 143 144 static void __dead2 sunxi_system_reset(void) 145 { 146 gicv2_cpuif_disable(); 147 148 if (scpi_available) { 149 /* Send the system reset request to the SCP */ 150 uint32_t ret = scpi_sys_power_state(scpi_system_reboot); 151 152 if (ret == SCP_OK) { 153 wfi(); 154 } 155 156 ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret); 157 } 158 159 /* Reset the whole system when the watchdog times out */ 160 mmio_write_32(SUNXI_WDOG0_CFG_REG, 1); 161 /* Enable the watchdog with the shortest timeout (0.5 seconds) */ 162 mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1); 163 /* Wait for twice the watchdog timeout before panicking */ 164 mdelay(1000); 165 166 ERROR("PSCI: System reset failed\n"); 167 panic(); 168 } 169 170 static int sunxi_validate_power_state(unsigned int power_state, 171 psci_power_state_t *req_state) 172 { 173 unsigned int power_level = psci_get_pstate_pwrlvl(power_state); 174 unsigned int type = psci_get_pstate_type(power_state); 175 176 assert(req_state != NULL); 177 178 if (power_level > PLAT_MAX_PWR_LVL) 179 return PSCI_E_INVALID_PARAMS; 180 181 if (type == PSTATE_TYPE_STANDBY) { 182 /* Only one retention power state is supported. */ 183 if (psci_get_pstate_id(power_state) > 0) 184 return PSCI_E_INVALID_PARAMS; 185 /* The SoC cannot be suspended without losing state */ 186 if (power_level == SYSTEM_PWR_LVL) 187 return PSCI_E_INVALID_PARAMS; 188 for (unsigned int i = 0; i <= power_level; ++i) 189 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; 190 } else { 191 /* Only one off power state is supported. */ 192 if (psci_get_pstate_id(power_state) > 0) 193 return PSCI_E_INVALID_PARAMS; 194 for (unsigned int i = 0; i <= power_level; ++i) 195 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 196 } 197 /* Higher power domain levels should all remain running */ 198 for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i) 199 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; 200 201 return PSCI_E_SUCCESS; 202 } 203 204 static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint) 205 { 206 /* The non-secure entry point must be in DRAM */ 207 if (ns_entrypoint < SUNXI_DRAM_BASE) { 208 return PSCI_E_INVALID_ADDRESS; 209 } 210 211 return PSCI_E_SUCCESS; 212 } 213 214 static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state) 215 { 216 assert(req_state); 217 218 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) 219 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 220 } 221 222 static plat_psci_ops_t sunxi_psci_ops = { 223 .cpu_standby = sunxi_cpu_standby, 224 .pwr_domain_on = sunxi_pwr_domain_on, 225 .pwr_domain_off = sunxi_pwr_domain_off, 226 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish, 227 .system_off = sunxi_system_off, 228 .system_reset = sunxi_system_reset, 229 .validate_power_state = sunxi_validate_power_state, 230 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, 231 }; 232 233 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 234 const plat_psci_ops_t **psci_ops) 235 { 236 assert(psci_ops); 237 238 /* Program all CPU entry points. */ 239 for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) { 240 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu), 241 sec_entrypoint & 0xffffffff); 242 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu), 243 sec_entrypoint >> 32); 244 } 245 246 /* Check for a valid SCP firmware, and boot the SCP if found. */ 247 if (mmio_read_32(SUNXI_SCP_BASE) == SCP_FIRMWARE_MAGIC) { 248 /* Program SCP exception vectors to the firmware entrypoint. */ 249 for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) { 250 uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i); 251 uint32_t offset = SUNXI_SCP_BASE - vector; 252 253 mmio_write_32(vector, offset >> 2); 254 clean_dcache_range(vector, sizeof(uint32_t)); 255 } 256 /* Take the SCP out of reset. */ 257 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); 258 /* Wait for the SCP firmware to boot. */ 259 if (scpi_wait_ready() == 0) 260 scpi_available = true; 261 } 262 263 NOTICE("PSCI: System suspend is %s\n", 264 scpi_available ? "available via SCPI" : "unavailable"); 265 if (scpi_available) { 266 /* Suspend is only available via SCPI. */ 267 sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off; 268 sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish; 269 sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state; 270 } 271 272 *psci_ops = &sunxi_psci_ops; 273 274 return 0; 275 } 276