Merge "feat(libc): add printf support for space padding" into integration

Merge "fix(cpus): workaround for Neoverse V2 erratum 2618597" into integration

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I23a81275d1e40cae39e6897093d6cdd3e11c08ea
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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feat(libc): add printf support for space padding

This patch makes printf capable of padding strings with spaces
to their left, allowing right-aligning numeric values and strings.
It uses the same wi

feat(libc): add printf support for space padding

This patch makes printf capable of padding strings with spaces
to their left, allowing right-aligning numeric values and strings.
It uses the same width field for the format specifier as in the
original libc function : %<width><type> (e.g.: %10d pads an
integer value with spaces to the left to complete 10 characters).

Change-Id: Ib7b5519dae17742181352ce58e507a05ba5250d4
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "fix(cpus): workaround for Neoverse V2 erratum 2662553" into integration

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workarou

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workaround for Cortex-X3 erratum 2779509

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Merge "fix(errata): check for SCU before accessing DSU" into integration

fix(errata): check for SCU before accessing DSU

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system va

fix(errata): check for SCU before accessing DSU

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3 memory
system variant is used, there won't be any L3 cache, snoop filter, and
SCU logic present hence no system control register will be present.
Hence check SCU presence before accessing DSU register for DSU_2313941
errata.

(commit message taken from commit
942013e1dd57429432cd71cfe121d702e3c52465 by Pramod Kumar
<pramod.kumar@broadcom.com> just errata number changed)

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I38cee6085d6e49ba23de95b3de08bc98798ab2b3

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fix(cpus): workaround for Neoverse V2 erratum 2662553

Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size s

fix(cpus): workaround for Neoverse V2 erratum 2662553

Neoverse V2 erratum 2662553 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I3bc43e7299c17db8a6771a547515ffb2a172fa0f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1

fix(cpus): workaround for Cortex-A78C erratum 2743232

Cortex-A78C erratum 2743232 is a Cat B erratum that applies
to revisions r0p1 and r0p2 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: Ic62579c2dd69b7a8cbbeaa936f45b2cc9436439a
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL

fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 2779509

Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUA

fix(cpus): workaround for Cortex-X3 erratum 2779509

Cortex-X3 erratum 2779509 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is
to set chicken bit CPUACTLR3_EL1[47], this might have a small
impact on power and has negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

Removed the PLAT_RSS_NOT_SUPPORTED build option, which was initially
introduced for building the Base AEM FVP platform platform with RSS.
H

refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

Removed the PLAT_RSS_NOT_SUPPORTED build option, which was initially
introduced for building the Base AEM FVP platform platform with RSS.
However, we now have a well-defined TC2 platform with RSS, making it
unnecessary to keep this flag.

Note -
Theoretically this is a breaking change. Other platforms could be
using the PLAT_RSS_NOT_SUPPORTED build option. Among upstream platforms,
only the Base AEM FVP uses it right now but we don't know about
downstream platforms.

Change-Id: I931905a4c6ac1ebe3895ab6e0287d0fa07721707
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(xlat): set MAX_PHYS_ADDR to total mapped physical region" into integration

Merge changes Ia72b2542,I1eba5671 into integration

* changes:
chore(compiler-rt): update compiler-rt source files
chore(zlib): update zlib to version 1.3

Merge "refactor(cm): introduce INIT_UNUSED_NS_EL2 macro" into integration

Merge "fix(smccc): ensure that mpidr passed through SMC is valid" into integration

refactor(cm): introduce INIT_UNUSED_NS_EL2 macro

Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL

refactor(cm): introduce INIT_UNUSED_NS_EL2 macro

Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL2. Platforms without NS-EL2 in use
must enable this flag.

BREAKING CHANGE: Initialisation code for handoff from EL3 to NS-EL1
disabled by default. Platforms which do that need to enable this macro
going forward

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I61431cc4f7e2feb568d472828e5fd79cc73e51f5

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chore(compiler-rt): update compiler-rt source files

Update the compiler-rt source files to the tip of llvm-project [1].

[1] https://github.com/llvm/llvm-project/commit/ab97b89d03a7

Signed-off-by:

chore(compiler-rt): update compiler-rt source files

Update the compiler-rt source files to the tip of llvm-project [1].

[1] https://github.com/llvm/llvm-project/commit/ab97b89d03a7

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia72b25423896a530bf5bb68ff067184b2314e2be

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chore(zlib): update zlib to version 1.3

Update the zlib source files to the latest tagged version 1.3 [1].

[1] https://github.com/madler/zlib/tree/v1.3

Signed-off-by: Manish Pandey <manish.pandey2

chore(zlib): update zlib to version 1.3

Update the zlib source files to the latest tagged version 1.3 [1].

[1] https://github.com/madler/zlib/tree/v1.3

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1eba5671efab75699e68fc2f2aa9400d0f5aba7d

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fix(smccc): ensure that mpidr passed through SMC is valid

There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr v

fix(smccc): ensure that mpidr passed through SMC is valid

There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr validation check consistent across SMC calls, do
this check as part of SMC argument validation.

This patch introduce a helper function is_valid_mpidr() to validate
mpidr and call it as part of validating SMC arguments at starting of
SMC handlers (which expect mpidr as an argument).

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I11ea50e22caf17896cf4b2059b87029b2ba136b1

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Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround fo

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround for Neoverse N2 erratum 2340933
fix(cpus): workaround for Neoverse N2 erratum 2346952

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fix(xlat): set MAX_PHYS_ADDR to total mapped physical region

Currently some platforms set PLAT_XLAT_TABLES_DYNAMIC=0 and
define it unconditionally also in platform Makefiles.
Due to this when PLAT_X

fix(xlat): set MAX_PHYS_ADDR to total mapped physical region

Currently some platforms set PLAT_XLAT_TABLES_DYNAMIC=0 and
define it unconditionally also in platform Makefiles.
Due to this when PLAT_XLAT_TABLES_DYNAMIC=0 the limits for
MAX_PHYS_ADDR is wrongly set to the whole physical address space size.
Instead of definition the value of PLAT_XLAT_TABLES_DYNAMIC is checked
to set MAX_PHYS_ADDR to total mapped physical region.

Reference: plat/nvidia/tegra/platform.mk

Change-Id: I7bd786aaa4b039951341d0337f694074345f717f
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55

fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[5

fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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