| 7c25a3a1 | 27-Jan-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore(cpus): remove redundant asserts
get_cpu_ops_ptr asserts that it didn't get 0 for a cpu_ops pointer. Its
callers don't need to do the same.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.
chore(cpus): remove redundant asserts
get_cpu_ops_ptr asserts that it didn't get 0 for a cpu_ops pointer. Its
callers don't need to do the same.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I547ac592949f74e153ef161015326f64aead2f28
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|
| e444763d | 17-Nov-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(cpus): shorten errata flag defines
The cpu-ops makefile has errata flag definition and flag processing done
per flag in separate parts in the file. Rework this to make a list and
do this in
refactor(cpus): shorten errata flag defines
The cpu-ops makefile has errata flag definition and flag processing done
per flag in separate parts in the file. Rework this to make a list and
do this in a much more concise way.
To ensure no flags were missed, a bash script [1] was used to verify all
errata flags made it across. Only the first few flags with different
naming were checked manually.
[1]:
sed -n "s/CPU_FLAG_LIST += ERRATA_\(.*\)/\1/p" lib/cpus/cpu-ops.mk > \
/tmp/new
git checkout origin/master
sed -n "s/ERRATA_\([[:alnum:]_-]*\)\s*?=0/\1/p" lib/cpus/cpu-ops.mk > \
/tmp/old
diff /tmp/old /tmp/new
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3b88af46838cc26f42d2c66b31f96c0855fa406c
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| a4c69581 | 15-Mar-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration |
| 42d4d3ba | 22-Nov-2022 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
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|
| 4c985e86 | 14-Mar-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integration |
| 2535e204 | 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
style: fix functions definitions
This is to fix old style functions definitions.
Change-Id: I094b1497dcf948d4d8de4d57d93878aa092ea053
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> |
| 521d4fe6 | 13-Mar-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "style: remove useless trailing semicolon and line continuations" into integration |
| f1c3eae9 | 02-Mar-2023 |
Sona Mathew <SonaRebecca.Mathew@arm.com> |
fix(cpus): workaround for Neoverse V1 errata 2743233
Neoverse V1 erratum 2743233 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround sets CPUACTLR5_EL1[56:55]
fix(cpus): workaround for Neoverse V1 errata 2743233
Neoverse V1 erratum 2743233 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround sets CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest
Change-Id: If51a6f4293fa8b5b35c44edd564ebb715ba309a1
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
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|
| 9a90d720 | 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
style: remove useless trailing semicolon and line continuations
found using checkpatch.pl[1]
[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl
S
style: remove useless trailing semicolon and line continuations
found using checkpatch.pl[1]
[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c
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|
| 66bf3ba4 | 28-Feb-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A78C erratum 2779484
Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.
The workaround is to set the CPUACTLR
fix(cpus): workaround for Cortex-A78C erratum 2779484
Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.
The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact on
performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed
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|
| a63332c5 | 28-Feb-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL
fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
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|
| b4fc0410 | 28-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "feat_state_part2" into integration
* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(t
Merge changes from topic "feat_state_part2" into integration
* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
fix(cpufeat): context-switch: move FGT availability check to callers
feat(cpufeat): extend check_feature() to deal with min/max
refactor(cpufeat): wrap CPU ID register field isolation
show more ...
|
| fc8d2d39 | 17-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detecti
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_TRF_FOR_NS=2), by splitting
is_feat_trf_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRF related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_trf_supported() function to guard its execution.
The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRF is an ARMv8.4 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: Ia97b01adbe24970a4d837afd463dc5506b7295a3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| ff491036 | 17-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_BRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime dete
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_BRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_BRBE_FOR_NS=2), by splitting
is_feat_brbe_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access BRBE related registers.
The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_BRBE is an ARMv9 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: I5f2e2c9648300f65f0fa9a5f8e2f34e73529d053
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| f5360cfa | 17-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime dete
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_TRBE_FOR_NS=2), by splitting
is_feat_trbe_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRBE related registers.
The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRBE is an ARMv9 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: Iee7f88ea930119049543a8a4a105389997e7692c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| de8c4892 | 15-Feb-2023 |
Andre Przywara <andre.przywara@arm.com> |
fix(cpufeat): context-switch: move FGT availability check to callers
To be inline with other features, and to allow the availability to be
checked for different contexts, move the FGT availability c
fix(cpufeat): context-switch: move FGT availability check to callers
To be inline with other features, and to allow the availability to be
checked for different contexts, move the FGT availability check out of
the save/restore functions. This is instead now checked at the caller.
Change-Id: I96e0638714f9d1b6fdadc1cb989cbd33bd48b1f6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| 766d78b1 | 27-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "mbedtls3_support" into integration
* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add b
Merge changes from topic "mbedtls3_support" into integration
* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add braces for if statement
feat(fvp): increase BL1_RW and BL2 size
feat(mbedtls): add support for mbedtls-3.3
refactor(crypto): avoid using struct mbedtls_pk_rsassa_pss_options
refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE
show more ...
|
| a8eadc51 | 11-Jan-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE
Currently we include MBEDTLS_CONFIG_FILE directly and if a custom
config file is used it will included.
However from mbedtls-3.x onwards it di
refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE
Currently we include MBEDTLS_CONFIG_FILE directly and if a custom
config file is used it will included.
However from mbedtls-3.x onwards it discourages usage of
MBEDTLS_CONFIG_FILE include directly, so to resolve this and keep 2.28
compatibility include version.h which would include the custom config
file if present and also would expose us with mbedtls-major-version
number which could be used for selecting features and functions for
mbedtls 2.28 or 3.3
Change-Id: I029992311be2a38b588ebbb350875b03ea29acdb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| da04341e | 14-Feb-2023 |
Chris Kay <chris.kay@arm.com> |
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.
This change introduces the period prefix to all specialized section
names.
BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 23af5965 | 14-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "bk/python_dependencies" into integration
* changes:
build(docs): update Python dependencies
fix(docs): make required compiler version == rather than >=
fix(deps): add
Merge changes from topic "bk/python_dependencies" into integration
* changes:
build(docs): update Python dependencies
fix(docs): make required compiler version == rather than >=
fix(deps): add missing aeabi_memset.S
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| bdedee5a | 09-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(deps): add missing aeabi_memset.S
This file provides __aeabi_memclr8 builtin which the Ubuntu 22.04
version of clang 14 needs to compile. Add it to prevent this oddity from
failing the build.
S
fix(deps): add missing aeabi_memset.S
This file provides __aeabi_memclr8 builtin which the Ubuntu 22.04
version of clang 14 needs to compile. Add it to prevent this oddity from
failing the build.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id67aa0abba4a27c51b3ed6bb1be84b4e803b44bf
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| f90fe02f | 29-Sep-2022 |
Chris Kay <chris.kay@arm.com> |
style: normalize linker script code style
There are a variety of code styles used by the various linker scripts
around the code-base. This change brings them in line with one another
and attempts to
style: normalize linker script code style
There are a variety of code styles used by the various linker scripts
around the code-base. This change brings them in line with one another
and attempts to make the scripts more friendly for skim-readers.
Change-Id: Ibee2afad0d543129c9ba5a8a22e3ec17d77e36ea
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| 904da6f1 | 10-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(context-mgmt): enable SCXTNUM access" into integration |
| d69a0bf2 | 10-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(mpam): run-time checks for mpam save/restore routines" into integration |
| af4fee04 | 10-Feb-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW config
refactor(fvp): rename the DTB info structure member
feat(fconf): rename 'ns-load-address' to 'secondary-load-address'
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