fix(cpus): workaround for Neoverse N1 erratum 925373

Neoverse N1 erratum 925373 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by disabling SPE p

fix(cpus): workaround for Neoverse N1 erratum 925373

Neoverse N1 erratum 925373 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by disabling SPE profiling, or by setting
CPUACTLR3_EL1[33] and CPUACTLR3_EL1[34] to 1 so that WFE and WFI
instructions are executed as NOP instructions. This workaround
potentially have power implications.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885747/latest

Change-Id: I0dd9170615858ad2ebefbf69b92630a03b2493c1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/cortex_a78-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78 erratum 4302972
fix(cpus): workaround for Cortex-A78 erratum 3888017
fix(cpus):

Merge changes from topic "xl/cortex_a78-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78 erratum 4302972
fix(cpus): workaround for Cortex-A78 erratum 3888017
fix(cpus): fix A78 workaround version for WORKAROUND_CVE_2024_5660
fix(cpus): workaround for Cortex-A78 erratum 1827429
fix(cpus): workaround for Cortex-A78 erratum 1515634
fix(cpus): workaround for Cortex-A78 erratum 1503072
fix(cpus): workaround for Cortex-A78 erratum 1492189
fix(cpus): workaround for Cortex-A78 erratum 1479939
fix(cpus): workaround for Cortex-A78 erratum 1467580

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fix(cpus): workaround for Cortex-A715 erratum 2285473

Cortex-A715 erratum 2285473 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting bit[1

fix(cpus): workaround for Cortex-A715 erratum 2285473

Cortex-A715 erratum 2285473 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting bit[12] in CPUACTLR3_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I6f3750507a8e166d99fe5ce83b0d9b7031604410
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2238661

Cortex-A715 erratum 2238661 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

The erratum can be avoided by setting bit[0]

fix(cpus): workaround for Cortex-A715 erratum 2238661

Cortex-A715 erratum 2238661 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

The erratum can be avoided by setting bit[0] in CPUACTLR_EL1. Setting
this bit is not expected to have a significant performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Ifbf9f2da57aa7fc48ff8ba0699cb7c21a86df4b5
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2275754

Cortex-A715 erratum 2275754 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting bit[2

fix(cpus): workaround for Cortex-A715 erratum 2275754

Cortex-A715 erratum 2275754 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting bit[20] in CPUACTLR2_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I561d70204cfc18c010e2bd35df96804e9ebaa303
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2284544

Cortex-A715 erratum 2284544 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting bit[2

fix(cpus): workaround for Cortex-A715 erratum 2284544

Cortex-A715 erratum 2284544 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting bit[20] in CPUACTLR2_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: If4340aa0b19a6fd5fafe466b0bc327ac68dfdbd0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2239006

Cortex-A715 erratum 2239006 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

The erratum can be avoided by setting bit[9]

fix(cpus): workaround for Cortex-A715 erratum 2239006

Cortex-A715 erratum 2239006 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

The erratum can be avoided by setting bit[9] in CPUACTLR2_EL1. Setting
this bit is not expected to have any significant performance impact
for test silicon.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I6ce87366079d16f256bf90086a2d8df72ff9fe28
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2292761

Cortex-A715 erratum 2292761 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Cortex-A715 erratum 2292761

Cortex-A715 erratum 2292761 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR4_EL1[13] to 1. Using
this workaround has no performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Ie2bddb8535a0070da1a58a7753ad3a95c5005646
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse N1 erratum 3888013

Neoverse N1 erratum 3888013 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, r4p1. It is still open.

The erratu

fix(cpus): workaround for Neoverse N1 erratum 3888013

Neoverse N1 erratum 3888013 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, r4p1. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1 to
disable linking multiple Non-Cacheable or Device GRE loads to the same
cache line read request; this may significantly reduce Non-Cacheable
and Device GRE read bandwidth for streaming workloads.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885747/latest

Change-Id: I69ce57376458649f164e88e482a7c59e1edf4fab
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse N1 erratum 1791580

Neoverse N1 erratum 1791580 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0. It is fixed in r4p1.

Software shou

fix(cpus): workaround for Neoverse N1 erratum 1791580

Neoverse N1 erratum 1791580 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0. It is fixed in r4p1.

Software should set CPUACTLR2_EL1[2] to force Atomic Store operations
to shareable write-back memory to be performed in the L1 data cache
rather than as far atomics on the interconnect.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885747/latest

Change-Id: I6f0d4eeb497e549df63b423a7e091b219912cf21
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 4302972

Cortex-A78 erratum 4302972 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2. It is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A78 erratum 4302972

Cortex-A78 erratum 4302972 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2. It is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: Ifc42ee54918ed06db21d3dd04d4969d5cc948c4e
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 3888017

Cortex-A78 erratum 3888017 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2. It is still open.

The erratum can be avoided by

fix(cpus): workaround for Cortex-A78 erratum 3888017

Cortex-A78 erratum 3888017 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1, which
will disable linking multiple Non-Cacheable or Device GRE loads to the
same read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: Ic67b8f39d8defdd681cf47209f8d292c924afe19
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): fix A78 workaround version for WORKAROUND_CVE_2024_5660

The errata CVE_2024_5660 is still open in Cortex-A78 so apply the
workaround regardless the CPU revision.

SDEN documentation:
http

fix(cpus): fix A78 workaround version for WORKAROUND_CVE_2024_5660

The errata CVE_2024_5660 is still open in Cortex-A78 so apply the
workaround regardless the CPU revision.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: I527cb6a2aaadc9e5eea245c16d10a78bf44f3b9c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 1827429

Cortex-A78 erratum 1827429 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.

This erratum can be avoided by setting

fix(cpus): workaround for Cortex-A78 erratum 1827429

Cortex-A78 erratum 1827429 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.

This erratum can be avoided by setting CPUECTLR_EL1[53] to 1, which
disables the allocation of splintered pages in the L2 TLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: I3f7124a3344201a8d679ec362cf455a4efe4f3be
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 1515634

Cortex-A78 erratum 1515634 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR_EL1[11] to one, which flushes the

fix(cpus): workaround for Cortex-A78 erratum 1515634

Cortex-A78 erratum 1515634 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR_EL1[11] to one, which flushes the L0 Macro-op cache for
all context synchronization events.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: Iace7bdbfee19c747ec616e2c1e983dd2eb6849e1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 1503072

Cortex-A78 erratum 1503072 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This issue can be worked around by using the i

fix(cpus): workaround for Cortex-A78 erratum 1503072

Cortex-A78 erratum 1503072 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This issue can be worked around by using the instruction patching
mechanism. The code sequence should be applied early in the boot
sequence prior to any of the possible errata conditions being met.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: If6459894ead4899de4de0c4a9d191430b7107abd
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 1492189

Cortex-A78 erratum 1492189 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

The workaround is to set CPUACTLR5_EL1[8] to 1

fix(cpus): workaround for Cortex-A78 erratum 1492189

Cortex-A78 erratum 1492189 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

The workaround is to set CPUACTLR5_EL1[8] to 1'b1. The workaround
might result in a small increase in core power consumption.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: I08ca75132a268be38728b8a588b8adbb1975dfa9
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 1479939

Cortex-A78 erratum 1479939 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Cortex-A78 erratum 1479939

Cortex-A78 erratum 1479939 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1 to
disable a performance feature. This should be done before enabling the
MMU.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: I553697b5d34da00298526ee0988f52dea8e9e93f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 1467580

Cortex-A78 erratum 1467580 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Instruction patching, through hardware registe

fix(cpus): workaround for Cortex-A78 erratum 1467580

Cortex-A78 erratum 1467580 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Instruction patching, through hardware registers, for an ERET
instruction prevents ERET instructions from entering into this
scenario.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest

Change-Id: I253c05431ea142c2be5472c2c228a6912143aa7b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76 erratum 3888013

Cortex-A76 erratum 3888013 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, r4p1. It is still open.

The erratum

fix(cpus): workaround for Cortex-A76 erratum 3888013

Cortex-A76 erratum 3888013 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, r4p1. It is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: If3f1963bd51a82cc2773d1b36093666c9dbb9fd9
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76 erratum 2356586

Cortex-A76 erratum 2356586 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, r4p1. It is still open.

Set CPUACTLR

fix(cpus): workaround for Cortex-A76 erratum 2356586

Cortex-A76 erratum 2356586 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, r4p1. It is still open.

Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches. There
might be a small performance degradation to this workaround for
certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: I0d69d4ac2620cfeb1f4a180225d70e7268c6caa7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1793423

Cortex-A710 erratum 1793423 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Cortex-A710 erratum 1793423

Cortex-A710 erratum 1793423 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR5_EL1[10] to 1. Setting
CPUACTLR5_EL1[10] to 1 will have a performance impact on workloads
that use LDP 64-bit variant.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I7015799210f048bd147c9ae687ca0f47579fee24
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1785648

Cortex-A710 erratum 1785648 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR2_EL1[2] to force atomic store o

fix(cpus): workaround for Cortex-A710 erratum 1785648

Cortex-A710 erratum 1785648 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR2_EL1[2] to force atomic store operations to write-back
memory to be performed in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I2efb410d6712a1265518daaa16e0caa2daa370da
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 3888014

Cortex-A76AE erratum 3888014 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1. It is still open.

The erratum can be avoided by se

fix(cpus): workaround for Cortex-A76AE erratum 3888014

Cortex-A76AE erratum 3888014 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1, which
disables linking multiple Non-Cacheable or Device GRE loads to the
same read request for the cache line. This might have a significant
performance impact on Non-Cacheable and Device GRE read bandwidth for
streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/latest

Change-Id: I70074c0c7f8845605df5709932dba80748332025
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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build: rename default_ones to set_ones

default_zeros is a shorthand to set a flag to 0 with `?=`. This is
useful because we want a safe value that we can do simple checks like
`ifneq (${SOME_FLAG},0

build: rename default_ones to set_ones

default_zeros is a shorthand to set a flag to 0 with `?=`. This is
useful because we want a safe value that we can do simple checks like
`ifneq (${SOME_FLAG},0)`.

default_ones' use case is a bit different. It is only used to "force" a
bunch of flags on, unless set on the commandline. It doesn't need to be
as gentle as default_zeros since its values are expected to be final.

So rename it to set_ones and change the ?= assignment to := to better
reflect this. This patch also inlines `default_one` as there were no
external callers to it.

Change-Id: I418db7a1d0186a55febd4fe3c928805ed8fcfca6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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