Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Neoverse-N3 erratum 3456111
fix(cpus): workaround for Neoverse-N2 erratum 3324339
fix(cpus)

Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Neoverse-N3 erratum 3456111
fix(cpus): workaround for Neoverse-N2 erratum 3324339
fix(cpus): workaround for Neoverse-N1 erratum 3324349

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fix(cpus): workaround for Neoverse-N3 erratum 3456111

Neoverse-N3 erratum 3456111 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.

This errata can be avoided by adding

fix(cpus): workaround for Neoverse-N3 erratum 3456111

Neoverse-N3 erratum 3456111 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973

Change-Id: I1685c2cacbe64ddf70501e8cce94b4fbf03f0ba0
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "feat(cpus): fix external LLC presence bit in Neoverse N3" into integration

feat(cpus): fix external LLC presence bit in Neoverse N3

Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
ext

feat(cpus): fix external LLC presence bit in Neoverse N3

Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
external LLC in Neoverse N3, so the bit will be cleared when
NEOVERSE_Nx_EXTERNAL_LLC is not enabled.

Change-Id: I1182aba5423e74748efd2571cc3817634ada748d
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the i

Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the init_cpu_data_ptr function
perf(cpus): inline the reset function
perf(cpus): inline the cpu_get_rev_var call
perf(cpus): inline cpu_rev_var checks
refactor(cpus): register DSU errata with the errata framework's wrappers
refactor(cpus): convert checker functions to standard helpers
refactor(cpus): convert the Cortex-A65 to use the errata framework
fix(cpus): declare reset errata correctly

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perf(cpus): make reset errata do fewer branches

Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and cach

perf(cpus): make reset errata do fewer branches

Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and caches will be empty so a branch to a workaround function must be
fetched from memory and that round trip is very slow. Then it also runs
with the I-cache off, which means that the loop to iterate over the
workarounds must also be fetched from memory on each iteration.

We can remove both branches. First, we can simply apply every erratum
directly instead of defining a workaround function and jumping to it.
Currently, no errata that need to be applied at both reset and runtime,
with the same workaround function, exist. If the need arose in future,
this should be achievable with a reset + runtime wrapper combo.

Then, we can construct a function that applies each erratum linearly
instead of looping over the list. If this function is part of the reset
function, then the only "far" branches at reset will be for the checker
functions. Importantly, this mitigates the slowdown even when an erratum
is disabled.

The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup
from PSCI calls that end in powerdown. This is roughly back to the
baseline of v2.9, before the errata framework regressed on performance
(or a little better). It is important to note that there are other
slowdowns since then that remain unknown.

Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "gr/errata_ICH_VMCR_EL2" into integration

* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3701767
fix(cpus): workaround for Neoverse-N3 erratum 3699563
fix(cp

Merge changes from topic "gr/errata_ICH_VMCR_EL2" into integration

* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3701767
fix(cpus): workaround for Neoverse-N3 erratum 3699563
fix(cpus): workaround for Neoverse-N2 erratum 3701773
fix(cpus): workaround for Cortex-X925 erratum 3701747
fix(cpus): workaround for Cortex-X4 erratum 3701758
fix(cpus): workaround for Cortex-X3 erratum 3701769
fix(cpus): workaround for Cortex-X2 erratum 3701772
fix(cpus): workaround for Cortex-A725 erratum 3699564
fix(cpus): workaround for Cortex-A720-AE erratum 3699562
fix(cpus): workaround for Cortex-A720 erratum 3699561
fix(cpus): workaround for Cortex-A715 erratum 3699560
fix(cpus): workaround for Cortex-A710 erratum 3701772
fix(cpus): workaround for accessing ICH_VMCR_EL2
chore(cpus): fix incorrect header macro

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fix(cpus): workaround for Neoverse-N3 erratum 3699563

Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open.

The workaround is for EL3 software that performs context save/restore
on a chan

fix(cpus): workaround for Neoverse-N3 erratum 3699563

Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973/latest/

Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "clean-up-errata-compatibility" into integration

* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "feat(cpus): support to update External LLC presence in Neoverse N3" into integration

feat(cpus): support to update External LLC presence in Neoverse N3

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is interna

feat(cpus): support to update External LLC presence in Neoverse N3

The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with the build option 'NEOVERSE_Nx_EXTERNAL_LLC'.

Change-Id: I2567283a55c0d6e2f9fd986b7dbab91c7a815d3d
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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Merge "chore: rename hermes to neoverse-n3" into integration

chore: rename hermes to neoverse-n3

Rename hermes cpu to Neoverse-N3

Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>