1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <cortex_a17.h> 11#include <cpu_macros.S> 12 13 .macro assert_cache_enabled 14#if ENABLE_ASSERTIONS 15 ldcopr r0, SCTLR 16 tst r0, #SCTLR_C_BIT 17 ASM_ASSERT(eq) 18#endif 19 .endm 20 21func cortex_a17_disable_smp 22 ldcopr r0, ACTLR 23 bic r0, #CORTEX_A17_ACTLR_SMP_BIT 24 stcopr r0, ACTLR 25 isb 26 dsb sy 27 bx lr 28endfunc cortex_a17_disable_smp 29 30func cortex_a17_enable_smp 31 ldcopr r0, ACTLR 32 orr r0, #CORTEX_A17_ACTLR_SMP_BIT 33 stcopr r0, ACTLR 34 isb 35 bx lr 36endfunc cortex_a17_enable_smp 37 38 /* ---------------------------------------------------- 39 * Errata Workaround for Cortex A17 Errata #852421. 40 * This applies only to revision <= r1p2 of Cortex A17. 41 * Inputs: 42 * r0: variant[4:7] and revision[0:3] of current cpu. 43 * Shall clobber: r0-r3 44 * ---------------------------------------------------- 45 */ 46func errata_a17_852421_wa 47 /* 48 * Compare r0 against revision r1p2 49 */ 50 mov r2, lr 51 bl check_errata_852421 52 cmp r0, #ERRATA_NOT_APPLIES 53 beq 1f 54 ldcopr r0, CORTEX_A17_IMP_DEF_REG1 55 orr r0, r0, #(1<<24) 56 stcopr r0, CORTEX_A17_IMP_DEF_REG1 571: 58 bx r2 59endfunc errata_a17_852421_wa 60 61func check_errata_852421 62 mov r1, #0x12 63 b cpu_rev_var_ls 64endfunc check_errata_852421 65 66func check_errata_cve_2017_5715 67#if WORKAROUND_CVE_2017_5715 68 mov r0, #ERRATA_APPLIES 69#else 70 mov r0, #ERRATA_MISSING 71#endif 72 bx lr 73endfunc check_errata_cve_2017_5715 74 75#if REPORT_ERRATA 76/* 77 * Errata printing function for Cortex A17. Must follow AAPCS. 78 */ 79func cortex_a17_errata_report 80 push {r12, lr} 81 82 bl cpu_get_rev_var 83 mov r4, r0 84 85 /* 86 * Report all errata. The revision-variant information is passed to 87 * checking functions of each errata. 88 */ 89 report_errata ERRATA_A17_852421, cortex_a17, 852421 90 report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715 91 92 pop {r12, lr} 93 bx lr 94endfunc cortex_a17_errata_report 95#endif 96 97func cortex_a17_reset_func 98 mov r5, lr 99 bl cpu_get_rev_var 100 101#if ERRATA_A17_852421 102 bl errata_a17_852421_wa 103#endif 104 105#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 106 ldr r0, =workaround_bpiall_runtime_exceptions 107 stcopr r0, VBAR 108 stcopr r0, MVBAR 109 /* isb will be applied in the course of the reset func */ 110#endif 111 112 mov lr, r5 113 b cortex_a17_enable_smp 114endfunc cortex_a17_reset_func 115 116func cortex_a17_core_pwr_dwn 117 push {r12, lr} 118 119 assert_cache_enabled 120 121 /* Flush L1 cache */ 122 mov r0, #DC_OP_CISW 123 bl dcsw_op_level1 124 125 /* Exit cluster coherency */ 126 pop {r12, lr} 127 b cortex_a17_disable_smp 128endfunc cortex_a17_core_pwr_dwn 129 130func cortex_a17_cluster_pwr_dwn 131 push {r12, lr} 132 133 assert_cache_enabled 134 135 /* Flush L1 caches */ 136 mov r0, #DC_OP_CISW 137 bl dcsw_op_level1 138 139 bl plat_disable_acp 140 141 /* Exit cluster coherency */ 142 pop {r12, lr} 143 b cortex_a17_disable_smp 144endfunc cortex_a17_cluster_pwr_dwn 145 146declare_cpu_ops cortex_a17, CORTEX_A17_MIDR, \ 147 cortex_a17_reset_func, \ 148 cortex_a17_core_pwr_dwn, \ 149 cortex_a17_cluster_pwr_dwn 150