| d4a770a9 | 23-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): update nand driver to match GHRD design" into integration |
| ae6542f6 | 22-May-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(st-bsec): add driver for the new IP version BSEC3
This driver is used for the new version of the BSEC peripheral used
on STM32MP25.
Change-Id: I38ca0db22d06704769c994c6806ccd80b17dde6e
Signed-
feat(st-bsec): add driver for the new IP version BSEC3
This driver is used for the new version of the BSEC peripheral used
on STM32MP25.
Change-Id: I38ca0db22d06704769c994c6806ccd80b17dde6e
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| e6a0994c | 23-Jan-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st-bsec-otp" into integration
* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm
Merge changes from topic "st-bsec-otp" into integration
* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm32mp2): add missing include
feat(st): do not directly call BSEC functions in common code
feat(st): use stm32_get_otp_value_from_idx() in BL31
refactor(st): update test for closed chip
refactor(st-bsec): improve BSEC driver
refactor(st): use dashes for BSEC node names
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| a773f412 | 15-Nov-2023 |
Girisha Dengi <girisha.dengi@intel.com> |
fix(intel): update nand driver to match GHRD design
Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.
Signed-off-by: Girisha Dengi <girisha.dengi@i
fix(intel): update nand driver to match GHRD design
Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1cb3dda43e767ba243fbe89bfa18818db321c5c2
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| 586701ce | 02-Oct-2019 |
Yann Gautier <yann.gautier@st.com> |
refactor(st-i2c): use fdt_read_uint32_default()
The function stm32_i2c_get_setup_from_fdt() was using fdt_getprop() to
to get some i2c node properties, and set a default value if the node
was not fo
refactor(st-i2c): use fdt_read_uint32_default()
The function stm32_i2c_get_setup_from_fdt() was using fdt_getprop() to
to get some i2c node properties, and set a default value if the node
was not found. The function fdt_read_uint32_default() already does
this in a simpler way.
Remove useless STM32_I2C_SPEED_DEFAULT.
Change-Id: I74c6295bb5765ee7c7e0a9ae020b741f1fe022a6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 0651b7be | 08-Sep-2023 |
Kathleen Capella <kathleen.capella@arm.com> |
feat(spmd): add FFA_MSG_SEND_DIR_RESP2
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_RESP2 interface.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: Ibd0546ecd71d004804e6e18b27a
feat(spmd): add FFA_MSG_SEND_DIR_RESP2
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_RESP2 interface.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: Ibd0546ecd71d004804e6e18b27a4728a21259fa0
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|
| cc6047b3 | 31-Jul-2023 |
Kathleen Capella <kathleen.capella@arm.com> |
feat(spmd): add FFA_MSG_SEND_DIR_REQ2
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_REQ2 interface.
Handler validates security states of sender/receiver pairs
and forwards the call to other world if ne
feat(spmd): add FFA_MSG_SEND_DIR_REQ2
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_REQ2 interface.
Handler validates security states of sender/receiver pairs
and forwards the call to other world if necessary.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I02a60362d8d9a50fcc0b6a84753cba274ba5eb1b
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|
| c7061045 | 14-Dec-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
refactor(st-bsec): improve BSEC driver
In order to ease the introduction of a new BSEC3 driver for STM32MP25,
the BSEC2 driver is reworked. Unused functions are removed. The
bsec_base global variabl
refactor(st-bsec): improve BSEC driver
In order to ease the introduction of a new BSEC3 driver for STM32MP25,
the BSEC2 driver is reworked. Unused functions are removed. The
bsec_base global variable is removed in favor of the macro BSEC_BASE.
A rework is also done around function checking the state of BSEC.
Change-Id: I1ad76cb67333ab9a8fa1d65db34d74a712bf1190
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| a65c5ba3 | 20-Dec-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X3 erratum 2266875
Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]
fix(cpus): workaround for Cortex-X3 erratum 2266875
Cortex-X3 erratum 2266875 is a Cat B erratum that applies to
all revisions <= r1p0 and is fixed in r1p1. The workaround is to
set CPUACTLR_EL1[22]=1 which will cause the CFP instruction to
invalidate all branch predictor resources regardless of context.
SDEN Documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I9c610777e222f57f520d223bb03fc5ad05af1077
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| 638a6f8e | 19-Jan-2023 |
Shruti Gupta <shruti.gupta@arm.com> |
feat(el3-spmc): add support for FFA_CONSOLE_LOG
Add support for FFA_CONSOLE_LOG in EL3 SPMC,
Disallow forwarding FFA_CONSOLE_LOG across worlds.
Add support for FFA_CONSOLE_LOG in FFA_FEATURES.
Inpu
feat(el3-spmc): add support for FFA_CONSOLE_LOG
Add support for FFA_CONSOLE_LOG in EL3 SPMC,
Disallow forwarding FFA_CONSOLE_LOG across worlds.
Add support for FFA_CONSOLE_LOG in FFA_FEATURES.
Input parameters:
w0/x0 - FFA_CONSOLE_LOG_32/64
w1/x1 - Character count
w2/x2-w7/x7 - 24 or 48 characters depending upon whether a SMC32 or
SMC64 FID was used.
Output parameters in case of success:
w0/x0 - FFA_SUCCESS
Output parameters in case of error:
w0/x0 - FFA_ERROR
w2/x2 - NOT_SUPPORTED: ABI is not implemented
INVALID_PARAMETERS: Parameters are incorrectly encoded
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I004c043729e77d1b9aa396c42d25c73d9268169a
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|
| eefa45cf | 10-Jan-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(context-mgmt): align the memory address of EL2 context registers" into integration |
| 8c56a788 | 09-Jan-2024 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(context-mgmt): align the memory address of EL2 context registers
EL2 registers are 8 byte wide and are allocated continuous memory.
After moving MPAM_EL2 registers out of the EL2 struct, the sec
fix(context-mgmt): align the memory address of EL2 context registers
EL2 registers are 8 byte wide and are allocated continuous memory.
After moving MPAM_EL2 registers out of the EL2 struct, the section
of memory, assigned to MPAM registers in EL2 registers structure has
to be removed.
Henceforth, this patch addresses this issue and cleans up the unsued memory.
Change-Id: I3425b43add0755ff1f5cb803cd5fa667082e7814
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 0f0fd499 | 26-Dec-2023 |
Rohit Mathew <Rohit.Mathew@arm.com> |
fix(rotpk): move rotpk definitions out of arm_def.h
The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing t
fix(rotpk): move rotpk definitions out of arm_def.h
The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing them to avoid a direct dependency on arm_def.h. For a clean
platform port of arm_def.h, none of the source files should directly
include arm_def.h; instead, they should include the platform header
which would indirectly include the required definitions.
Presently, the rotpk module has a source file that directly includes
arm_def.h. This could lead to compilation issues if the platform
incorporating the rotpk module has a separate implementation of some or
all of the definitions in arm_def.h file. To address this, move the
relevant definitions out of arm_def.h and into rotpk_def.h.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I9e8b0d319391f9a167af5c69a7b2d42ac488e7b4
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|
| b77f55d6 | 15-Dec-2023 |
Rohit Mathew <Rohit.Mathew@arm.com> |
feat(cpu): add support for Poseidon V CPU
Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by
a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache.
This enhan
feat(cpu): add support for Poseidon V CPU
Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by
a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache.
This enhancement ensures compatibility with RD-Fremont and similar
platforms utilizing Poseidon V CPUs.
CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Icdcc5f57c62855b2ec54c58a401d3bf09f292189
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|
| 61a29682 | 15-Dec-2023 |
Rohit Mathew <Rohit.Mathew@arm.com> |
fix(cpu): correct variant name for default Poseidon CPU
Update the Poseidon CPU variant name to "POSEIDON VNAE" in alignment
with the MIDR 0x410FD830. This adjustment reflects the accurate
designati
fix(cpu): correct variant name for default Poseidon CPU
Update the Poseidon CPU variant name to "POSEIDON VNAE" in alignment
with the MIDR 0x410FD830. This adjustment reflects the accurate
designation for the default Poseidon CPU and allows for seamless support
of other variants in the future.
CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I48183290ffc2889d6ae000d3aa423c0ee5e4d211
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|
| 6d511a8c | 03-Jan-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(platforms): update SZ_* macros
Use unsigned long values for __aarch64__ version of SZ_* macros.
This allows using masks with ~SZ_* without losing the 32 upper bits.
Signed-off-by: Yann Gautier
feat(platforms): update SZ_* macros
Use unsigned long values for __aarch64__ version of SZ_* macros.
This allows using masks with ~SZ_* without losing the 32 upper bits.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie485fad65088df17e6c489ebb3159220d6add647
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|
| bfef8b90 | 08-Nov-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(context-mgmt): report context memory usage
This patch provides a reporting functionality to display the memory
consumed by the context in each security state and for each exception
level. Flag
feat(context-mgmt): report context memory usage
This patch provides a reporting functionality to display the memory
consumed by the context in each security state and for each exception
level. Flag PLATFORM_REPORT_CTX_MEM_USE enables or disables this
feature.
Change-Id: I1515366bf87561dcedf2b3206be167804df681d4
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 9acff28a | 06-Oct-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
build(mpam): add new build option CTX_INCLUDE_MPAM_REGS
New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This opt
build(mpam): add new build option CTX_INCLUDE_MPAM_REGS
New build option CTX_INCLUDE_MPAM_REGS is added to select
if the firmware needs to save the MPAM EL2 registers during world
switches. This option is currently disabled as MPAM is only
enabled for NS world.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie2e5e184cdb65f7e1a98d8fe81590253fd859679
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| ac4f6aaf | 08-Nov-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(cm): move MPAM3_EL3 reg to per world context
Refactor MPAM3_EL3 to be world-specific, eliminating redundant cross-CPU
value duplication and reducing memory footprint.
Signed-off-by: Arvind
refactor(cm): move MPAM3_EL3 reg to per world context
Refactor MPAM3_EL3 to be world-specific, eliminating redundant cross-CPU
value duplication and reducing memory footprint.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iddf020a5462737e01ac35e4f2b2b204a8759fafb
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| 4087ed6c | 11-Dec-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
refactor(cm): reset the cptr_el3 before perworld context setup
Currently, the registers which are maintained per-world, does not
take into account the reset value while configuring the context for
t
refactor(cm): reset the cptr_el3 before perworld context setup
Currently, the registers which are maintained per-world, does not
take into account the reset value while configuring the context for
the respective world.
This leads to an issue, wherein the register retains the same value
across world switch, which is an error.
This patch addresses this problem, by configuring the register
(cptr_el3) precisely according to the world, the cpu is in
execution via resetting it before initializing the world specific context.
Change-Id: I592d82af373155fca67eed109c199341c305f0b9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 7b78a022 | 19-Dec-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Cortex-A520 erratum 2858100" into integration |
| 34db3531 | 09-Dec-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Cortex-A520 erratum 2858100
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUAC
fix(cpus): workaround for Cortex-A520 erratum 2858100
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677
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| 1da798a9 | 18-Dec-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(handoff): enhance transfer list library" into integration |
| 40fd755b | 04-Oct-2023 |
Raymond Mao <raymond.mao@linaro.org> |
feat(handoff): enhance transfer list library
Define new transfer entry TL_TAG_OPTEE_PAGABLE_PART for OP-TEE.
Add API for achieving handoff args from transfer entries.
Add API for dumping the transfe
feat(handoff): enhance transfer list library
Define new transfer entry TL_TAG_OPTEE_PAGABLE_PART for OP-TEE.
Add API for achieving handoff args from transfer entries.
Add API for dumping the transfer list.
Add tl->flags, tl->reserved and TL_FLAGS_HAS_CHECKSUM to align to
the spec update.
Update TL signature to 4a0f_b10b to align to the spec update.
Minor fixes for the coding and comment style.
Change-Id: I0e159672e4ef4c50576f70b82e1b7bae08407acc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
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| f03bfc30 | 10-Dec-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Cortex-A520 erratum 2630792
Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1
fix(cpus): workaround for Cortex-A520 erratum 2630792
Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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