Merge "feat(smccc): enable support for FEAT_MEC" into integration

Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7

feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7924
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_op

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C
fix(aarch32): make get_cpu_ops_ptr() PCS compliant

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Merge "feat(cpus): add support for Canyon CPU" into integration

fix(cpus): inform the compiler that struct cpu_ops is aligned

The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it m

fix(cpus): inform the compiler that struct cpu_ops is aligned

The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it must
assume the worst. As a result, it's scared to do 64 bit loads and must
do 8 single byte loads that it then can combine together.

Well, the cpu assembly macros take care to align the cpu_ops entries to
a word boundary so we can propagate that information to the structure
definition as well and removed the compiler's paranoia.

Change-Id: Id38d6f1b92527b8a414cfbb856a5a82c76a1b1a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of assembly was
that the get_cpu_ops_ptr() function was not PCS compliant and needed a
wrapper to do that instead. That has now been fixed so move this to C so
it's more readable and more optimise-able by the compiler.

Change-Id: I5fcfe8ddb122dd35d58adc6d44a7484c5c595815
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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Merge "fix(drtm): remove plat_system_reset()" into integration

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fe

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fec5fd38f07a8081f35d94

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feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

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Merge changes from topic "xlnx_misra_fix_gen_pmuv3" into integration

* changes:
fix(lib): modify function to have single return
fix(lib): use 64-bit constants in MDCR_EL2 bit macros

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that i

fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that is only implemented on FVP, that conflicts with it.
This sometimes results in failed builds.

DRTM remediation ends with a platform reset. However, there is currently
an error message printed that this is not supported. In this case, the
correct thing to do is to panic and as such this hook is not needed.

Further, the correct sequence to reset the system is different and is
only fully implemented by psci_system_reset(). This is a portable
implementation supported by a wide variety of platform.

So remove plat_system_reset(). Once DRTM remediation properly supports
resetting, the psci_system_reset() function should be used to achieve
reset correctly and portably.

Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec61

feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec6160bd794f48e3c41718ecce0ec88a

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feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-

feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I845e8863ca6e757b1da6f30833e6ec10e21b0667

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Merge "fix(intel): fix SDMMC driver when sdmclk running at 200MHz" into integration

Merge "fix(intel): fix eMMC driver issues in boot flow on agilex5" into integration

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(fvp): factor out interrupt information from the dts

The FVP_Base models are all identical. Individual components can be
swapped out without affecting the rest of the system. In order to not

refactor(fvp): factor out interrupt information from the dts

The FVP_Base models are all identical. Individual components can be
swapped out without affecting the rest of the system. In order to not
diverge too much, factor as much common stuff out but leave out
interrupt information so that it can be swapped out.

Change-Id: I4ce5b627c7ca00d98f10eba888cc1bf4d61880a9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(lib): use 64-bit constants in MDCR_EL2 bit macros

Updated bitmask definitions in MDCR_EL2 macros to use ULL(1) instead
of U(1), ensuring the left operand in shift operations is of an
appropriate

fix(lib): use 64-bit constants in MDCR_EL2 bit macros

Updated bitmask definitions in MDCR_EL2 macros to use ULL(1) instead
of U(1), ensuring the left operand in shift operations is of an
appropriate width. This avoids MISRA C:2012 Rule 12.2 violations,
which prohibit shifting a value by more than 7 bits when the left-
hand operand is an unsigned int.

Change-Id: I279fb33c2ef714367953d53e61456490cd7c798b
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717

fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717afe1fa0de167aae532f8b8de03b1c
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correc

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.

Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.

Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.

eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.

Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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