1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ 8 #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ 9 10 #include <mtcmos_common.h> 11 #include <platform_def.h> 12 13 #define RTFF_SAVE BIT(24) 14 #define RTFF_NRESTORE BIT(25) 15 #define RTFF_CLK_DIS BIT(28) 16 17 #define VLPCFG_REG_BASE (0x1C00C000) 18 #define POWERON_CONFIG_EN (SPM_BASE + 0x0) 19 #define UFS0_PWR_CON (SPM_BASE + 0x0E10) 20 #define UFS0_PHY_PWR_CON (SPM_BASE + 0x0E14) 21 22 #define PERISYS_PROTECT_EN_STA_0 (INFRACFG_AO_BASE + 0x0C80) 23 #define PERISYS_PROTECT_EN_STA_0_SET (INFRACFG_AO_BASE + 0x0C84) 24 #define PERISYS_PROTECT_EN_STA_0_CLR (INFRACFG_AO_BASE + 0x0C88) 25 #define PERISYS_PROTECT_RDY_STA_0 (INFRACFG_AO_BASE + 0x0C8C) 26 #define VLP_TOPAXI_PROTECTEN (VLPCFG_REG_BASE + 0x0210) 27 #define VLP_TOPAXI_PROTECTEN_SET (VLPCFG_REG_BASE + 0x0214) 28 #define VLP_TOPAXI_PROTECTEN_CLR (VLPCFG_REG_BASE + 0x0218) 29 #define VLP_TOPAXI_PROTECTEN_STA1 (VLPCFG_REG_BASE + 0x0220) 30 31 #define UFS0_PROT_STEP1_0_MASK BIT(5) 32 #define UFS0_PROT_STEP2_0_MASK BIT(4) 33 #define UFS0_PROT_STEP3_0_MASK BIT(6) 34 35 static const struct bus_protect ufs0_bus_prot_set_table[] = { 36 {VLP_TOPAXI_PROTECTEN_SET, VLP_TOPAXI_PROTECTEN_STA1, UFS0_PROT_STEP1_0_MASK}, 37 {PERISYS_PROTECT_EN_STA_0_SET, PERISYS_PROTECT_RDY_STA_0, UFS0_PROT_STEP2_0_MASK}, 38 {VLP_TOPAXI_PROTECTEN_SET, VLP_TOPAXI_PROTECTEN_STA1, UFS0_PROT_STEP3_0_MASK}, 39 }; 40 41 static const struct bus_protect ufs0_bus_prot_clr_table[] = { 42 {VLP_TOPAXI_PROTECTEN_CLR, 0x0, UFS0_PROT_STEP3_0_MASK}, 43 {PERISYS_PROTECT_EN_STA_0_CLR, 0x0, UFS0_PROT_STEP2_0_MASK}, 44 {VLP_TOPAXI_PROTECTEN_CLR, 0x0, UFS0_PROT_STEP1_0_MASK}, 45 }; 46 47 static const struct bus_protect ufs0_phy_bus_prot_set_table[] = {}; 48 static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = {}; 49 50 #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ */ 51