chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "xlnx_misra_fix_gen_common" into integration

* changes:
fix(bl31): add missing curly braces
fix(xilinx): match function type as its declared
fix(platforms): typedef op

Merge changes from topic "xlnx_misra_fix_gen_common" into integration

* changes:
fix(bl31): add missing curly braces
fix(xilinx): match function type as its declared
fix(platforms): typedef operands to match data type
fix(platforms): declare unused parameters as void
fix(platforms): add essential bool type
fix(platforms): fix misra violation 10.1

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Merge "refactor(lib): add cache unit alignment attribute to cpu_context_t" into integration

Merge "feat(cpus): fix external LLC presence bit in Neoverse N3" into integration

Merge "fix(cpufeat): configure CPTR_EL2.ZEN and CPTR_EL2.TZ to match Linux" into integration

fix(platforms): typedef operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a

fix(platforms): typedef operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I1ed3b7fc1866b34f1086e449ffe648f53c33b008
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(cpus): fix external LLC presence bit in Neoverse N3

Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
ext

feat(cpus): fix external LLC presence bit in Neoverse N3

Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
external LLC in Neoverse N3, so the bit will be cleared when
NEOVERSE_Nx_EXTERNAL_LLC is not enabled.

Change-Id: I1182aba5423e74748efd2571cc3817634ada748d
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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fix(lib): align round_up with MISRA 10.1 and 10.8

Adjust integer literals and operand types to ensure
consistent unsigned usage and eliminate implicit
type mismatches. This enhances compliance with

fix(lib): align round_up with MISRA 10.1 and 10.8

Adjust integer literals and operand types to ensure
consistent unsigned usage and eliminate implicit
type mismatches. This enhances compliance with MISRA
10.1 and 10.8.

Change-Id: Icf07313ae36d2a58bfb38c390c988ddcd913953f
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an

build(measured-boot)!: move to ext event log lib

Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
re

Merge changes from topic "bk/no_blx_setup" into integration

* changes:
fix: replace stray BL2_AT_EL3 with RESET_TO_BL2
refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint
refactor: unify blx_setup() and blx_main()
fix(bl2): unify the BL2 EL3 and RME entrypoints

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feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR mac

feat(ff-a): bump SPMD FF-A version

The Hafnium SPM version bumped to FF-A v1.3, alongside
the TF-A SPMD.
EL3 SPMC was kept under the v1.2 version with its own
set of FFA_VERSION_SPMC_MAJOR/MINOR macros.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I0494738b9978ad72b3316a24d7811096c53f952b

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Merge changes I32c5be5d,I15a652a0 into integration

* changes:
fix(qemu): add reason parameter to MEC update
refactor(rmmd): modify MEC update call to meet FIRME

fix(cpufeat): configure CPTR_EL2.ZEN and CPTR_EL2.TZ to match Linux

Linux Documentation/arch/arm64/booting.rst states that:
"
For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
...
-

fix(cpufeat): configure CPTR_EL2.ZEN and CPTR_EL2.TZ to match Linux

Linux Documentation/arch/arm64/booting.rst states that:
"
For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
...
- If the kernel is entered at EL1 and EL2 is present:
- CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
- CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
"
Without these settings, Linux kernel hangs on boot when trying
to use SVE. Adjust the register settings to match Linux kernel
expectations.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I9a72810dd902b08f9c61f157cc31e603aad2f73a

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refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[1] https://developer.arm.com/documentation/den0149/1-0alp0/

Change-Id: I15a652a021561edca16e79d127e6f08975cf1361
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have co

fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have copied arm_def.h and would have been
missed at some point. Update that too.

Change-Id: I28123186bb4b69c5d5154dcdd24e5dee9d9e33b8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint

We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection.

refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint

We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection. Well, this is
irrelevant for sp_min and not really appropriate for PSCI. So move it to
the bl31_warmboot() function to reflect this correctly and bring the
feature detection a bit earlier, hopefully spotting more errors.

This allows for a pair of minor cleanups - we can pass the core_pos to
psci_warmboot_entrypoint() without having to refetch it, and we can put
the pauth enablement in cm_manage_extensions_el3() along with all
others. The call of that function is kept after the MMU is turned on so
that we have nicer (coherent) access to cpu_data.

Change-Id: Id031cfa0e1d8fe98919a14f9db73eb5bc9e00f67
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: unify blx_setup() and blx_main()

All BLs have a bl_setup() for things that need to happen early, a fall
back into assembly and then bl_main() for the main functionality. This
was necessary

refactor: unify blx_setup() and blx_main()

All BLs have a bl_setup() for things that need to happen early, a fall
back into assembly and then bl_main() for the main functionality. This
was necessary in order to fiddle with PAuth related things that tend to
break C calls. Since then PAuth's enablement has seen a lot of
refactoring and this is now worked around cleanly so the distinction can
be removed. The only tradeoff is that this requires pauth to not be used
for the top-level main function.

There are two main benefits to doing this: First, code is easier to
understand as it's all together and the entrypoint is smaller. Second,
the compiler gets to see more of the code and apply optimisations
(importantly LTO).

Change-Id: Iddb93551115a2048988017547eb7b8db441dbd37
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(spmd): support for FFA_ABORT invocation from SWd

SPMC can propagate abort handling to SPMD when an SP specifies suitable
abort action in its manifest. SPMD panics upon receiving FFA_ABORT from

feat(spmd): support for FFA_ABORT invocation from SWd

SPMC can propagate abort handling to SPMD when an SP specifies suitable
abort action in its manifest. SPMD panics upon receiving FFA_ABORT from
SPMC.

Change-Id: I3b573fdfc203c3446b1d629f579e333162d5ff72
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(bl2): unify the BL2 EL3 and RME entrypoints

BL2 has 3(!) entrypoints:
1) the regular EL1 entrypoint (once per AArch)
2) an EL3 entrypoint
3) an EL3 entrypoint with RME

The EL1 and EL3 entryp

fix(bl2): unify the BL2 EL3 and RME entrypoints

BL2 has 3(!) entrypoints:
1) the regular EL1 entrypoint (once per AArch)
2) an EL3 entrypoint
3) an EL3 entrypoint with RME

The EL1 and EL3 entrypoints are quite distinct so it's useful to keep
them separate. But the EL3 and RME entrypoints are conceptually
identical just configured differently and having slightly different
assumptions (eg whether we can rely on BL1). So put them together with
only the configuration as a difference. This has a few benefits:
* makes the naming consistent - BL2 always runs at EL1, BL2_EL3 always
runs at EL3. This is most important for the linker script.
* paves the way for ENABLE_RME and RESET_TO_BL2 to coexist.
* allows for more general refactors

Currently, ENABLE_RME and RESET_TO_BL2 are mutually exclusive (from a
makefile constraint) so the checks are simplified to one or the other as
there is no danger of their simultaneous use.

Change-Id: Iecffab2ff3a0bd7823f8277d9f66e22e4f42cc8c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(lib): add cache unit alignment attribute to cpu_context_t

This patch ensures that the dirty cache lines associated with a single
CPU's context are contained within that core, preventing the

refactor(lib): add cache unit alignment attribute to cpu_context_t

This patch ensures that the dirty cache lines associated with a single
CPU's context are contained within that core, preventing them from
being shared with other CPUs. The alignment applied to cpu_context_t
is consistent with the existing alignment for cpu_data_t.

Change-Id: I4973cd46fe85724f61cd83e4d26ec366671061e2
Signed-off-by: Noah Woo <namyoon@google.com>

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Merge "feat(spmd): add FFA_NS_RES_INFO_GET ABI" into integration

Merge "feat(el3-spmc): parse and report VM availability messages" into integration

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505

feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505aab1ba9e8c
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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fix(smccc): cleanup unused declaration

Remove check_wa_cve_2024_7881() declaration left behind by patch
fd04156eb792963cb21144063e421d074efa6386.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakas

fix(smccc): cleanup unused declaration

Remove check_wa_cve_2024_7881() declaration left behind by patch
fd04156eb792963cb21144063e421d074efa6386.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iae81e0bcbd2feb2b72a4e4e8fd27a27ae00c9cb4

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