feat(smccc): clear scr_el3.nse in smccc_arch_feature_availability

Clear the SCR_EL3.NSE bit from the bitmask used in
SMCCC_ARCH_FEATURE_AVAILABILITY for RME.

This bit is set when FEAT_RME=1, and if

feat(smccc): clear scr_el3.nse in smccc_arch_feature_availability

Clear the SCR_EL3.NSE bit from the bitmask used in
SMCCC_ARCH_FEATURE_AVAILABILITY for RME.

This bit is set when FEAT_RME=1, and if not excluded, it leads to
an assertion failure due to unexpected bits being detected.

Change-Id: I399f63adc4814c4404705985b0816783e4626dda
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge "fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2" into integration

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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feat(stm32mp2): add RIF dt-binding defines

Add defines for RIF sub-system configuration (RIFSC, RISAB, RISAF,
RISUP and RIMU). List RIFSC identifiers in a platform-specific file.

Signed-off-by: Nic

feat(stm32mp2): add RIF dt-binding defines

Add defines for RIF sub-system configuration (RIFSC, RISAB, RISAF,
RISUP and RIMU). List RIFSC identifiers in a platform-specific file.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I770fb7d1866caf899171c80cb6ce65735ac97fc9

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feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region

feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region definition through DT.

Change-Id: I1bca9c0a89af88a72651e1a71e3f8950807eec40
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(dt-bindings): add MCE DT bindings for STM32MP13

This makes the region definition easier in DT, with explicit parameters.

Change-Id: I4e3f6e6d31288ccec807f3fc71544d8cf39ef1e5
Signed-off-by: Nic

feat(dt-bindings): add MCE DT bindings for STM32MP13

This makes the region definition easier in DT, with explicit parameters.

Change-Id: I4e3f6e6d31288ccec807f3fc71544d8cf39ef1e5
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instanc

feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instance for the TF-A
purpose as it needs only one to work. The others are activated because
needed by specific IPs.

Seed errors are now also checked after null data read. The Reference
Manual recommends to always verify that RNG_DR is different from zero.
Because when it is the case a seed error can occur between RNG_SR
polling and RND_DR output reading (rare event).

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Ie4d7f01f4ffe5a9e2d0e5e7317b008edd3b80a17

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Merge "fix(console): ensured proper bitwise shift operation" into integration

fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or f

fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or forwards a different set of registers,
depending on the FF-A version of the source and destination.
E.g. a call from a v1.1 caller to a v1.2 destination will zero
out the extended registers, which is different from the old behavior
of forwarding everything to EL2 SPMC, but only x0-x7 to the EL3 SPMC.

Change-Id: Ic31755af0fbb117b0ed74565fba9decebab353c4
Signed-off-by: Jay Monkman <jmonkman@google.com>
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width o

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width of the left operand. This ensures
compliance with MISRA C 2012 Rule 12.2.

Change-Id: I1a4ed9366bd9ab773c4a5f6798508ead991593d2
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "feat(smccc): introduce TPM Start SMC" into integration

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MP

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)

TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)

Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3

Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SP

feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SPM_MM module which converts into a MM_COMMUNICATE
to interact with Secure partition.

TPM Start method is mentioned in TCG ACPI spec section 3.3.1
https://trustedcomputinggroup.org/wp-content/uploads/TCG-ACPI-Specification-Version-1.4-Revision-15_pub.pdf

As this patch introduces a new sub service, increment minor version
of Vendor EL3 service.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I61698018e6bc33c9b389ac905fe158810af21bfa

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fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o

fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replaced usage of 'unsigned int' with 'size_t' to ensure type
consistency and prevent assignment to a narrower or different
essential type.

Change-Id: I79501e216a04753ebd005d64375357b9332440d9
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I7a2565ce6b8beb71dc9c711327ab72ce825111cc
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "feat(locks): add non-blocking spinlock_try() API" into integration

refactor(cm): gather per-world context management to the same place

The per-world calls are disparate - they get called in different places,
are guarded in different ways, and the code is apart.

Si

refactor(cm): gather per-world context management to the same place

The per-world calls are disparate - they get called in different places,
are guarded in different ways, and the code is apart.

Since they just need to be called once at boot, add a function that we
can call from BL31 and be done with it.

Change-Id: Id0ade302e35f2b00ca37c552a53038942ab7b58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(lib): add mmio read with timeout

In several cases, drivers poll a register using a blocking 'while'
or 'for' loop without a timeout mechanism. Introducing a timeout
would be beneficial, as it a

feat(lib): add mmio read with timeout

In several cases, drivers poll a register using a blocking 'while'
or 'for' loop without a timeout mechanism. Introducing a timeout
would be beneficial, as it allows the system to log an error and
delegate the decision to the caller - whether to continue execution
or halt with a panic.

To address this, the mmio_read_poll_timeout() helper can be used. It
exits with -ETIMEDOUT if the timeout is reached, or 0 on success.
Additionally, the final value read from the register is stored in the
'val' variable, avoiding the need for an extra read after polling
completes.

Change-Id: I2ef53299b12ece6bc7be0e1234d5c2708e36ecf9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "build(handoff)!: switch to LibTL submodule" into integration

Merge "feat(dsu): support power control and autonomous powerdown config" into integration

fix(common): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(common): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I350ba1dfd1af872c6d237aa7b46221fc10a2ef67
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

Merge "fix(libc): replace true-false with explicit comparisons" into integration

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

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build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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