Merge "feat(spmd): add FFA_NS_RES_INFO_GET ABI" into integration

Merge "feat(el3-spmc): parse and report VM availability messages" into integration

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505

feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505aab1ba9e8c
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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fix(smccc): cleanup unused declaration

Remove check_wa_cve_2024_7881() declaration left behind by patch
fd04156eb792963cb21144063e421d074efa6386.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakas

fix(smccc): cleanup unused declaration

Remove check_wa_cve_2024_7881() declaration left behind by patch
fd04156eb792963cb21144063e421d074efa6386.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iae81e0bcbd2feb2b72a4e4e8fd27a27ae00c9cb4

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Merge "feat(smccc): enable support for FEAT_MEC" into integration

Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7

feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7924
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_op

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C
fix(aarch32): make get_cpu_ops_ptr() PCS compliant

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Merge "feat(cpus): add support for Canyon CPU" into integration

fix(cpus): inform the compiler that struct cpu_ops is aligned

The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it m

fix(cpus): inform the compiler that struct cpu_ops is aligned

The only way to access a cpu_ops structure is through a pointer returned
from assembly so the compiler can't know its alignment and it must
assume the worst. As a result, it's scared to do 64 bit loads and must
do 8 single byte loads that it then can combine together.

Well, the cpu assembly macros take care to align the cpu_ops entries to
a word boundary so we can propagate that information to the structure
definition as well and removed the compiler's paranoia.

Change-Id: Id38d6f1b92527b8a414cfbb856a5a82c76a1b1a8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of

refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C

The difference between AArch32 and AArch64 is insignificant and the
usage is identical. The only thing that required the use of assembly was
that the get_cpu_ops_ptr() function was not PCS compliant and needed a
wrapper to do that instead. That has now been fixed so move this to C so
it's more readable and more optimise-able by the compiler.

Change-Id: I5fcfe8ddb122dd35d58adc6d44a7484c5c595815
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

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Merge "fix(drtm): remove plat_system_reset()" into integration

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fe

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fec5fd38f07a8081f35d94

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feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol

Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration

* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type

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Merge changes from topic "xlnx_misra_fix_gen_pmuv3" into integration

* changes:
fix(lib): modify function to have single return
fix(lib): use 64-bit constants in MDCR_EL2 bit macros

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that i

fix(drtm): remove plat_system_reset()

The name plat_system_reset() has been in use for some time by a mediatek
platform (in plat/mediatek/mt8173/plat_pm.c). However, DRTM added a
global hook, that is only implemented on FVP, that conflicts with it.
This sometimes results in failed builds.

DRTM remediation ends with a platform reset. However, there is currently
an error message printed that this is not supported. In this case, the
correct thing to do is to panic and as such this hook is not needed.

Further, the correct sequence to reset the system is different and is
only fully implemented by psci_system_reset(). This is a portable
implementation supported by a wide variety of platform.

So remove plat_system_reset(). Once DRTM remediation properly supports
resetting, the psci_system_reset() function should be used to achieve
reset correctly and portably.

Change-Id: Ia4e150c51aeec613838464fbb0e1d0542f19ccab
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec61

feat(scmi): add base protocol agent API

Support protocol attributes and discover agents

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3879f703ec6160bd794f48e3c41718ecce0ec88a

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feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-

feat(scmi): update version to 3.0

Update version to 3.0 to align with latest scmi spec implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I845e8863ca6e757b1da6f30833e6ec10e21b0667

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Merge "fix(intel): fix SDMMC driver when sdmclk running at 200MHz" into integration

Merge "fix(intel): fix eMMC driver issues in boot flow on agilex5" into integration

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sasc

feat(fvp): add a GICv5 device tree

Tested with Linux v6.17-rc1, it boots as long as cpu idle is disabled.

Change-Id: Iadeb157e9d911c4228dc62c5610676f4c07f6c11
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Lorenzo Pieralisi <lorenzo.pieralisi2@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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