Merge changes from topic "aarch32_debug_aborts" into integration

* changes:
feat(stm32mp1): add plat_report_*_abort functions
feat(debug): add helpers for aborts on AARCH32
feat(debug): add AA

Merge changes from topic "aarch32_debug_aborts" into integration

* changes:
feat(stm32mp1): add plat_report_*_abort functions
feat(debug): add helpers for aborts on AARCH32
feat(debug): add AARCH32 CP15 fault registers

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feat(ethos-n)!: add support for SMMU streams

The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these

feat(ethos-n)!: add support for SMMU streams

The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.

To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.

The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277

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feat(debug): add helpers for aborts on AARCH32

New helper functions are created to handle data & prefetch aborts
in AARCH32. They call platform functions, just like what
report_exception is doing.
A

feat(debug): add helpers for aborts on AARCH32

New helper functions are created to handle data & prefetch aborts
in AARCH32. They call platform functions, just like what
report_exception is doing.
As extended MSR/MRS instructions (to access lr_abt in monitor mode)
are only available if CPU (Armv7) has virtualization extension,
the functions branch to original report_exception handlers if this is
not the case.
Those new helpers are created mainly to distinguish data and prefetch
aborts, as they both share the same mode.
This adds 40 bytes of code.

Change-Id: I5dd31930344ad4e3a658f8a9d366a87a300aeb67
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(debug): add AARCH32 CP15 fault registers

For an easier debug on Aarch32, in case of abort, it is useful to access
DFSR, IFSR, DFAR and IFAR CP15 registers.

Change-Id: Ie6b5a2882cd701f76e9d455e

feat(debug): add AARCH32 CP15 fault registers

For an easier debug on Aarch32, in case of abort, it is useful to access
DFSR, IFSR, DFAR and IFAR CP15 registers.

Change-Id: Ie6b5a2882cd701f76e9d455ec43bd4b0fbe3cc78
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(cpu): use the updated IP name for Demeter CPU

Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the u

refactor(cpu): use the updated IP name for Demeter CPU

Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.

Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f

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Merge changes from topic "st_uart_updates" into integration

* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFI

Merge changes from topic "st_uart_updates" into integration

* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
feat(st): add trace for early console
fix(stm32mp1): enable crash console in FIQ handler
feat(st-uart): add initialization with the device tree
refactor(stm32mp1): move DT_UART_COMPAT in include file
feat(stm32mp1): configure the serial boot load address
fix(stm32mp1): update the FIP load address for serial boot
refactor(st): configure baudrate for UART programmer
refactor(st-uart): compute the over sampling dynamically

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fix(ufs): retry commands on unit attention

Unit Attention Condition (UAC) gets set on a warm reset. Sending any
command (other than INQUIRY and REPORT LUNs) clears UAC, so its good to
add some retri

fix(ufs): retry commands on unit attention

Unit Attention Condition (UAC) gets set on a warm reset. Sending any
command (other than INQUIRY and REPORT LUNs) clears UAC, so its good to
add some retries when UAC is encountered

Signed-off-by: Anand Saminathan <anans@google.com>
Change-Id: Ia03b916d68565d0f3d25086b7f6d8c51d557b64f

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feat(rss): add new comms protocols

The current comms protocol (where arguments and return data is embedded
into the MHU message) is now protocol v0. Protocol v1 embeds pointers
into the message, and

feat(rss): add new comms protocols

The current comms protocol (where arguments and return data is embedded
into the MHU message) is now protocol v0. Protocol v1 embeds pointers
into the message, and has the RSS retrieve the data via DMA.

Change-Id: I08d7f09c4eaea673769fde9eee194447a99f1b78
Signed-off-by: Raef Coles <raef.coles@arm.com>

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fix(libc): pri*ptr macros for aarch64

This fix solves problems with using PRI*PTR on aarch64 like so:
error: format '%x' expects argument of type 'unsigned int', but
argument 3 has type 'uintptr_t'

fix(libc): pri*ptr macros for aarch64

This fix solves problems with using PRI*PTR on aarch64 like so:
error: format '%x' expects argument of type 'unsigned int', but
argument 3 has type 'uintptr_t' {aka 'long unsigned int'}

Change-Id: I135d3e5cea5459f138b20331b5e9472e2e9e566c
Signed-off-by: K <kayo@illumium.org>

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Merge "refactor(libc): clean up dependencies in libc" into integration

refactor(st-uart): compute the over sampling dynamically

The parameter over_sampling of stm32_uart_init_s is not required
as it can be computed dynamically from clock rate of the serial
device and t

refactor(st-uart): compute the over sampling dynamically

The parameter over_sampling of stm32_uart_init_s is not required
as it can be computed dynamically from clock rate of the serial
device and the requested baudrate.

Oversampling by 8 is allowed only for higher speed
(up to clock_rate / 8) to reduce the maximum receiver tolerance
to clock deviation.

This patch update the driver, the serial init struct and the
only user, the stm32cubeprogrammer over uart support.

Change-Id: I422731089730a288defeb7fa49886db65d0902b2
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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Merge "fix(bl31): fix validate_el3_interrupt_rm preprocessor usage" into integration

refactor(libc): clean up dependencies in libc

- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert

refactor(libc): clean up dependencies in libc

- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.

Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568

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Merge "feat(pauth): add/modify helpers to support QARMA3" into integration

fix(bl31): fix validate_el3_interrupt_rm preprocessor usage

Fix the "#if defined(FOO)" usage introduced by commit 7c2fe62f1
("fix(bl31): allow use of EHF with S-EL2 SPMC") since the defines are
alwa

fix(bl31): fix validate_el3_interrupt_rm preprocessor usage

Fix the "#if defined(FOO)" usage introduced by commit 7c2fe62f1
("fix(bl31): allow use of EHF with S-EL2 SPMC") since the defines are
always passed as -DFOO=0 or as -DFOO=1. The "#if defined(FOO)" will now
always be true which is wrong.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I84fb144debc9899727a1fc021acdd59b4a6f0171

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Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL

Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL1 SGIs

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feat(services): add a SPD for ProvenCore

Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3

feat(services): add a SPD for ProvenCore

Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3af6a6f65791655685a7bc80070673c9f3

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feat(plat/arm/css): add interrupt handler for reboot request

Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into

feat(plat/arm/css): add interrupt handler for reboot request

Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.

In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.

Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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refactor(psci): move psci_do_pwrdown_sequence() out of private header

Move the psci_do_pwrdown_sequence() function declaration from PSCI
private header to common header. The psci_do_pwrdown_sequence

refactor(psci): move psci_do_pwrdown_sequence() out of private header

Move the psci_do_pwrdown_sequence() function declaration from PSCI
private header to common header. The psci_do_pwrdown_sequence is
required to support warm reset, where each CPU need to execute the
powerdown sequence.

Change-Id: I298e7a120be814941fa91c0b001002a080e56263
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(plat/arm/css): add per-cpu power down support for warm reset

Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY

feat(plat/arm/css): add per-cpu power down support for warm reset

Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.

Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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fix(gicv3): update the affinity mask to 8 bit

The GIC ICC_SGI0R_EL1 register's affinity fields are 8bit wide for GIC
v3 and v4. Fix the SGIR_AFF_MASK variable accordingly.

Change-Id: I09f3fdd006708

fix(gicv3): update the affinity mask to 8 bit

The GIC ICC_SGI0R_EL1 register's affinity fields are 8bit wide for GIC
v3 and v4. Fix the SGIR_AFF_MASK variable accordingly.

Change-Id: I09f3fdd006708b40162776620f82abcfc6c3f782
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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feat(gic): add APIs to raise NS and S-EL1 SGIs

This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI

Signed-off-by: Florian

feat(gic): add APIs to raise NS and S-EL1 SGIs

This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI

Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I6f262dd1da1d77fec3f850eb74189e726b8e24da

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Merge "fix(cpus): workaround for Cortex-A710 2216384" into integration

chore: use tabs for indentation

This patch changes the definition of image_info_t to follow the TF-A
coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-styl

chore: use tabs for indentation

This patch changes the definition of image_info_t to follow the TF-A
coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I17af22b4ba60b41cf0b5fa84ac47beeb1536edcc

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Merge changes from topic "fix_fip_in_emmc_boot" into integration

* changes:
fix(st): add max size for FIP in eMMC boot part
feat(mmc): get boot partition size