1 /* 2 * Copyright (c) 2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TRAP_HANDLE_H 8 #define TRAP_HANDLE_H 9 10 #include <stdbool.h> 11 #include <context.h> 12 13 #define ISS_SYSREG_OPCODE_MASK 0x3ffc1eUL 14 #define ISS_SYSREG_REG_MASK 0x0003e0UL 15 #define ISS_SYSREG_REG_SHIFT 5U 16 #define ISS_SYSREG_DIRECTION_MASK 0x000001UL 17 18 #define TRAP_RET_UNHANDLED -1 19 #define TRAP_RET_REPEAT 0 20 #define TRAP_RET_CONTINUE 1 21 22 #ifndef __ASSEMBLER__ 23 static inline unsigned int get_sysreg_iss_rt(uint64_t esr) 24 { 25 return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT; 26 } 27 28 static inline bool is_sysreg_iss_write(uint64_t esr) 29 { 30 return !(esr & ISS_SYSREG_DIRECTION_MASK); 31 } 32 33 /** 34 * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs 35 * @esr_el3: The content of ESR_EL3, containing the trap syndrome information 36 * @ctx: Pointer to the lower EL context, containing saved registers 37 * 38 * Called by the exception handler when a synchronous trap identifies as a 39 * system register trap (EC=0x18). ESR contains the encoding of the op[x] and 40 * CRm/CRn fields, to identify the system register, and the target/source 41 * GPR plus the direction (MRS/MSR). The lower EL's context can be altered 42 * by the function, to inject back the result of the emulation. 43 * 44 * Return: indication how to proceed with the trap: 45 * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic 46 * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction 47 * (repeating it) 48 * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction 49 * (continuing after it) 50 */ 51 int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); 52 53 #endif /* __ASSEMBLER__ */ 54 55 #endif 56