feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fe

feat(spmd): add FFA_NS_RES_INFO_GET ABI

Call should be forwarded to the SPMC from the NWd,
but not the other way around.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic0951ffc6610c31f94fec5fd38f07a8081f35d94

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feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

This patch adds support for getting the SoC name string
using the SMCCC_ARCH_SOC_ID interface. The SoC name query
was introduced in SMCCC versi

feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

This patch adds support for getting the SoC name string
using the SMCCC_ARCH_SOC_ID interface. The SoC name query
was introduced in SMCCC version 1.6. It is available only
through SMC64 calls.

A new function ID, SMCCC_GET_SOC_NAME, is added. It returns
the SoC name as a null-terminated ASCII string, spread across
registers X1 to X17 in little endian order.
The total length is 136 bytes, including the null byte.
Any space after the null terminator is filled
with zeros.

A platform hook plat_get_soc_name() is added to return the
SoC name. A weak default version is also provided that returns
SMC_ARCH_CALL_NOT_SUPPORTED for platforms that do not support
this feature.

The name should follow the SMCCC rule that it must not expose
any information that is not already reported
by the SoC version and revision calls.

Reference: https://developer.arm.com/documentation/den0028/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idc69997c509bcbfb1cecb38ed1003b29627ade4b

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fix(cm): disable SPE/TRBE correctly

SPE and TRBE are unusual features. They have multi-bit enables whose
function is not immediately apparent and disabling them is not
straightforward.

While attemp

fix(cm): disable SPE/TRBE correctly

SPE and TRBE are unusual features. They have multi-bit enables whose
function is not immediately apparent and disabling them is not
straightforward.

While attempting to figure this out, the disables were made a mess of.
Patch fc7dca72b began changing the owning security state of SPE and
TRBE. This was first used in patch 79c0c7fac0 with calls to
spe_disable() and trbe_disbale(). However, patch 13f4a2525 reverted the
security state ownership, making the spe_disable() and trbe_disable()
redundant and their comments incorrect - the DoS protection is achieved
by the psb/tsb barriers on context switch, introduces separately in
f80887337 and 73d98e375.

Those patches got the behaviour full circle to what it was in fc7dca72b
so the disables can be fully removed for clarity.

However, the original method for disabling these features is not fully
correct - letting the "disabled" state be all zeroes made the features
seem enabled for secure world but they would trap. That is not a problem
while secure world doesn't use them, but could lead to some confusing
debugging in the future. NS and Realm worlds were not affected. This
patch fully establishes the pattern for SPE and TRBE's enablement,
documents it, and implements it such.

The description comments in the features boil down to 2 rules. There is
a third rule possible:
3. To enable TRBE/SPE for world X with a dirty buffer:
* world X owns the buffer
* trapping enabled
This is not listed as it would not work correctly with
SMCCC_ARCH_FEATURE_AVAILABILITY which relies on trapping to be disabled
to report correctly. If that is ever implemented, the SMCCC
implementation should be considered too.

Change-Id: I5588a3d5fc074c2445470954d8c3b172bec77d43
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(smccc): clear scr_el3.nse in smccc_arch_feature_availability

Clear the SCR_EL3.NSE bit from the bitmask used in
SMCCC_ARCH_FEATURE_AVAILABILITY for RME.

This bit is set when FEAT_RME=1, and if

feat(smccc): clear scr_el3.nse in smccc_arch_feature_availability

Clear the SCR_EL3.NSE bit from the bitmask used in
SMCCC_ARCH_FEATURE_AVAILABILITY for RME.

This bit is set when FEAT_RME=1, and if not excluded, it leads to
an assertion failure due to unexpected bits being detected.

Change-Id: I399f63adc4814c4404705985b0816783e4626dda
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or f

fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or forwards a different set of registers,
depending on the FF-A version of the source and destination.
E.g. a call from a v1.1 caller to a v1.2 destination will zero
out the extended registers, which is different from the old behavior
of forwarding everything to EL2 SPMC, but only x0-x7 to the EL3 SPMC.

Change-Id: Ic31755af0fbb117b0ed74565fba9decebab353c4
Signed-off-by: Jay Monkman <jmonkman@google.com>
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SP

feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SPM_MM module which converts into a MM_COMMUNICATE
to interact with Secure partition.

TPM Start method is mentioned in TCG ACPI spec section 3.3.1
https://trustedcomputinggroup.org/wp-content/uploads/TCG-ACPI-Specification-Version-1.4-Revision-15_pub.pdf

As this patch introduces a new sub service, increment minor version
of Vendor EL3 service.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I61698018e6bc33c9b389ac905fe158810af21bfa

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feat(lfa): add LFA holding pen logic

Add LFA holding logic to be used by the LFA activate SMC call to manage
CPU rendezvous. All CPUs are expected to invoke the LFA activate call
for the rendezvous,

feat(lfa): add LFA holding pen logic

Add LFA holding logic to be used by the LFA activate SMC call to manage
CPU rendezvous. All CPUs are expected to invoke the LFA activate call
for the rendezvous, until then, they will remain on a holding lock.
When the final CPU calls LFA activate, it will release the holding
lock after completing the activation process on that CPU, allowing
the activation process on secondary CPUs to proceed.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Iff9e40dd87420245fe5844e286d0685c1f0db289

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feat(lfa): add initial implementation for LFA_ACTIVATE

This patch introduces the overall handling of the LFA_ACTIVATE call,
including input validation and invocation flow.
While this covers the core

feat(lfa): add initial implementation for LFA_ACTIVATE

This patch introduces the overall handling of the LFA_ACTIVATE call,
including input validation and invocation flow.
While this covers the core implementation, per-component-specific
handling will be developed in a separate patch. The respective
component callbacks are invoked as part of this logic.

Change-Id: Ie9d4584fc0c0abc9a9faffed62165b4461efed3a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(lfa): add initial implementation for LFA_PRIME

This patch introduces the overall handling of the LFA_PRIME call,
including input validation and invocation flow.
While this covers the core imple

feat(lfa): add initial implementation for LFA_PRIME

This patch introduces the overall handling of the LFA_PRIME call,
including input validation and invocation flow.
While this covers the core implementation, per-component-specific
handling will be developed in a separate patch. The respective
component callbacks are invoked as part of this logic.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie13d15d0a060ae5f9704991245d2a65c7d846047

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feat(lfa): implement LFA_GET_INVENTORY SMC

This implementation primarily retrieves activation-related flags for
a given fw_seq_id, including whether the firmware is activation
capable, whether an up

feat(lfa): implement LFA_GET_INVENTORY SMC

This implementation primarily retrieves activation-related flags for
a given fw_seq_id, including whether the firmware is activation
capable, whether an update is pending activation, whether it resets
the CPU during activation, whether CPU rendezvous is required, and the
firmware's UUID.
To support this, a platform API is called to determine whether an
update is available for the specified fw_seq_id, indicating its
pending activation status.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6e702a8b313386f5668027386845ff2dae9328e7

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feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build

Implement the LFA_GET_INFO SMC handler, which retrieves the
number of supported firmware components and performs initial
setup via the p

feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build

Implement the LFA_GET_INFO SMC handler, which retrieves the
number of supported firmware components and performs initial
setup via the platform APIs. This forms the entry point for
LFA usage and makes component metadata available for later use.

Update the build system to include LFA sources.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4016615a88706972eff6ea5777dda6d5a3a04074

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feat(rmm): add placeholder activator callbacks for LFA

Introduce the RMM component's activator structure for use in
LFA. The 'prime' and 'activate' callbacks currently return
LFA_WRONG_STATE as plac

feat(rmm): add placeholder activator callbacks for LFA

Introduce the RMM component's activator structure for use in
LFA. The 'prime' and 'activate' callbacks currently return
LFA_WRONG_STATE as placeholders.

These functions will be implemented in subsequent patches in
this series to support actual RMM component activation logic.

Change-Id: I899ff51e4065887b7b4bbfbaa827322c51cd215c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(bl31): add placeholder activator implementation for LFA

Introduce the BL31 component's activator structure with stub
implementations for the 'prime' and 'activate' callbacks.

Both callbacks cu

feat(bl31): add placeholder activator implementation for LFA

Introduce the BL31 component's activator structure with stub
implementations for the 'prime' and 'activate' callbacks.

Both callbacks currently return LFA_WRONG_STATE, indicating that
activation is not supported or allowed from BL31 in this context.

This activator is registered via get_bl31_activator(), allowing
the platform layer to wire it into the LFA framework.

Change-Id: I4279996b218d558a45cd99d5840f0e9f8ee97f90
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(lfa): add activation handler interface for component activation

Introduce `lfa_component_desc.h` defining structures and function
types to support component activation in LFA.

Includes:
- lfa_

feat(lfa): add activation handler interface for component activation

Introduce `lfa_component_desc.h` defining structures and function
types to support component activation in LFA.

Includes:
- lfa_component_status: to track per-component activation state
- lfa_component_ops: function table for prime and activate callbacks

The platform layer uses this interface to register component-specific
callbacks during initialization. These callbacks are implemented in
the component layer, and invoked by the LFA service to coordinate
activation by passing lfa_component_status details.

Change-Id: I141d49679bad3f134a2c5360342331604d2002f8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(lfa): create LFA SMC handler template

As per the specification v1.0[1], added all Live Firmware Activation
(LFA) SMCs, including their Function IDs (FIDs) and associated error
codes.
A dummy ha

feat(lfa): create LFA SMC handler template

As per the specification v1.0[1], added all Live Firmware Activation
(LFA) SMCs, including their Function IDs (FIDs) and associated error
codes.
A dummy handler function has been created as a template. Subsequent
patches will implement the handling of these SMCs.

[1]: https://developer.arm.com/documentation/den0147/latest/

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I5d6500dcff35aa4a438cd5f97f349cd57406ddce

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fix(drtm): set correct max region mask for DMA protection to 0xFFFF

Update `ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK` from `0xF` to
`0xFFFF` to correctly reflect the maximum number of supported D

fix(drtm): set correct max region mask for DMA protection to 0xFFFF

Update `ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK` from `0xF` to
`0xFFFF` to correctly reflect the maximum number of supported DMA
protection regions, as per the expected DRTM capability encoding.

The previous 4-bit mask limited the range to 16 regions, which is
insufficient and incorrect based on the spec's intention. This fix
extends the bitmask to 16 bits, allowing up to 65,535 regions if
supported in future implementations.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2531706f4b75125b510413870dfd4b1804e5adb6

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feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function

feat(smcc): introduce a new vendor_el3 service for ACS SMC handler

In preparation to add support for the Architecture Compliance Suite
SMC services, reserve a SMC ID and introduce a handler function.
Currently, an empty placeholder function is added and future support
will be introduced for the handler support.

More info on System ACS, please refer below link,
https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite

Signed-off-by: Nandan J <Nandan.J@arm.com>
Change-Id: Ib13ccae9d3829e3dcd1cd33c4a7f27efe1436d03

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Merge "feat(spe): add support for FEAT_SPE_FDS" into integration

Merge changes I0b0443d5,Ic454a87a into integration

* changes:
fix(gic): quote the correct flag on error
feat(lib): add a generic EXTRACT macro

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to

Merge changes from topic "fix_pmuv3p9_test" into integration

* changes:
fix(smccc): properly set RAS feature bit
fix(trng): allow FEAT_RNG_TRAP in dynamic fashion
feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY
feat(cpufeat): add support for PMUv3p9

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feat(lib): add a generic EXTRACT macro

The EXTRACT macro is useful to extract a named field from a numeric
value, usually a register. It is functionally identical to the `ubfx`
instruction and uses

feat(lib): add a generic EXTRACT macro

The EXTRACT macro is useful to extract a named field from a numeric
value, usually a register. It is functionally identical to the `ubfx`
instruction and uses the same #defines (REG_FIELD_SHIFT and
REG_FIELD_WIDTH).

This is the same macro that we use in tftf. It works well there and is
quite useful for manipulating register fields concisely.

This macro replaces the EXTRACT_FIELD macro. Their function is
identical, however, EXTRACT allows for easier interoperation with the
`ubfx` instruction, makes code more similar to tftf, and is more
concise.

Change-Id: Ic454a87af5e5fac108c7b7cb6b6804ec65a8d0e8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by

feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by: James Clark <james.clark2@arm.com>

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feat(trp): test el3-rmm ide km interface

This patch introduces test functions to the Test Realm Payload (TRP)
for performing basic sanity checks on the RMM-EL3 IDE KM support added
to EL3.

The prim

feat(trp): test el3-rmm ide km interface

This patch introduces test functions to the Test Realm Payload (TRP)
for performing basic sanity checks on the RMM-EL3 IDE KM support added
to EL3.

The primary goal of this patch is to only to verify the basic
functionality and ensure the implemented functions return the
correct return values.

The test uses random values for the ecam address, rootport ID,
IDE stream info, keys, and IV values.

Change-Id: Icf47627da9a6a7dd0d6e40e20ac94cc977072177
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM

feat(rmmd): el3-rmm ide key management interface

Patch introduces the EL3-RMM SMC Interface for Root Port
Key management as per RFC discussed here:
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface

Three IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()
- RMM_IDE_KEY_SET_STOP()
- RMM_IDE_KM_PULL_RESPONSE()

Due to the absence of root port support in FVP, we are
currently adding placeholders in this patch for the platform
APIs to return success irrespective of the arguments being passed
by the caller(Realms). The SMCs are guarded by
`RMMD_ENABLE_IDE_KEY_PROG` build flag and is disabled by default.
We expect that once the SMCs are stabilized, this build flag will
not be required anymore.

Change-Id: I9411eb7787dac2a207bd14710d251503bd9626ce
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(smccc): properly set RAS feature bit

The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be a

fix(smccc): properly set RAS feature bit

The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be accessed independently of the rest of the system's RAS
implementation status, BL31's RAS handling capabilities, or the way RAS
errors are routed by the firmware (FFH vs. KFH handling).
Tie the SCR_EL3.TERR bit to the right build symbol, since TF-A's
capability to handle RAS errors has nothing to do with lower EL's
accesses to those CPU system registers.

Change-Id: I4f06f915c0815c80058ec365139a8d818ba85721
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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