AArch64: Enable lower ELs to use pointer authentication

Pointer authentication is an Armv8.3 feature that introduces
instructions that can be used to authenticate and verify pointers.

Pointer authe

AArch64: Enable lower ELs to use pointer authentication

Pointer authentication is an Armv8.3 feature that introduces
instructions that can be used to authenticate and verify pointers.

Pointer authentication instructions are allowed to be accessed from all
ELs but only when EL3 explicitly allows for it; otherwise, their usage
will trap to EL3. Since EL3 doesn't have trap handling in place, this
patch unconditionally disables all related traps to EL3 to avoid
potential misconfiguration leading to an unhandled EL3 exception.

Fixes ARM-software/tf-issues#629

Change-Id: I9bd2efe0dc714196f503713b721ffbf05672c14d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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plat/arm: relocate the jump_if_cpu_midr macro.

macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic08

plat/arm: relocate the jump_if_cpu_midr macro.

macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

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Introduce object pool allocator

The object pool allocator provides a simplistic interface to manage
allocation in a fixed-size static array. The caller creates a static
"object pool" out of such an

Introduce object pool allocator

The object pool allocator provides a simplistic interface to manage
allocation in a fixed-size static array. The caller creates a static
"object pool" out of such an array and may then call pool_alloc() to
get the next available object within the pool. There is also a variant
to get multiple consecutive objects: pool_alloc_n().

Note that this interface does not provide any way to free the objects
afterwards. This is by design and it is not a limitation. We do not
want to introduce complexity induced by memory freeing, such as
use-after-free bugs, memory fragmentation and so on.

Change-Id: Iefc2e153767851fbde5841a295f92ae48adda71f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Remove some MISRA defects in common code

No functional changes.

Change-Id: I9638e02acb9b22eb794ebf45aad84348a710287e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Introduce RECLAIM_INIT_CODE build flag

This patch introduces a build flag "RECLAIM_INIT_CODE" to mark boot time
code which allows platforms to place this memory in an appropriate
section to be recla

Introduce RECLAIM_INIT_CODE build flag

This patch introduces a build flag "RECLAIM_INIT_CODE" to mark boot time
code which allows platforms to place this memory in an appropriate
section to be reclaimed later. This features is primarily targeted for
BL31. Appropriate documentation updates are also done.

Change-Id: If0ca062851614805d769c332c771083d46599194
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge pull request #1588 from satheesbalya-arm/sb1_2596_misra_tim_console

Fix misra warnings in delay timer and console drivers

Remove all other deprecated interfaces and files

Change-Id: Icd1cdd42afdc78895a9be6c46b414b0a155cfa63
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

xlat: Remove deprecated interfaces

Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

context_mgmt: Remove deprecated interfaces

Change-Id: I2d4a21a80a768bc422e9707e6d7e98d20a716275
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

PSCI: Remove deprecated file plat_psci_common.c

Change-Id: I9fd8016527ad7706494f34356fdae8efacef5f72
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

PSCI: Remove platform compatibility layer

Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.

PSCI: Remove platform compatibility layer

Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Fix misra warnings in delay timer and console drivers

Change-Id: I43d2b3a0f672b4902edec3d3a39ffedbb0a701a3
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

aarch32: PAR_ADDR_MASK should explicitly use BIT_64

PAR register used here is a 64 bit register.
On AARCH32 BIT macro is BIT_32.
PAR_ADDR_MASK should then use BIT_64 to avoid overflow.

Signed-off-b

aarch32: PAR_ADDR_MASK should explicitly use BIT_64

PAR register used here is a 64 bit register.
On AARCH32 BIT macro is BIT_32.
PAR_ADDR_MASK should then use BIT_64 to avoid overflow.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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ARMv7: Alias dmbld() to dmb()

'dmb ld' is not a recognized instruction for ARMv7. Since generic code
may use 'dmb ld', alias it to 'dmb' when building for ARMv7.

Change-Id: I502f360cb6412897ca9580b

ARMv7: Alias dmbld() to dmb()

'dmb ld' is not a recognized instruction for ARMv7. Since generic code
may use 'dmb ld', alias it to 'dmb' when building for ARMv7.

Change-Id: I502f360cb6412897ca9580b725d9f79469a7612e
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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cpus: denver: Implement static workaround for CVE-2018-3639

For Denver CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
dis

cpus: denver: Implement static workaround for CVE-2018-3639

For Denver CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
disable the mitigation at runtime.

This approach permanently mitigates the EL3 software stack only. Other
software components are responsible to enable it for their exception
levels.

TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3
and earlier:

* By setting bit 11 (Disable speculative store buffering) of
`ACTLR_EL3`

* By setting bit 9 (Disable speculative memory disambiguation) of
`ACTLR_EL3`

TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4
and later:

* By setting bit 18 (Disable speculative store buffering) of
`ACTLR_EL3`

* By setting bit 17 (Disable speculative memory disambiguation) of
`ACTLR_EL3`

Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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cpus: denver: reset power state to 'C1' on boot

Denver CPUs expect the power state field to be reset to 'C1'
during boot. This patch updates the reset handler to reset the
ACTLR_.PMSTATE field to 'C

cpus: denver: reset power state to 'C1' on boot

Denver CPUs expect the power state field to be reset to 'C1'
during boot. This patch updates the reset handler to reset the
ACTLR_.PMSTATE field to 'C1' state during CPU boot.

Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #1547 from semihalf-dabros-jan/semihalf-dabros-jan/fix_errmisc

AARCH64: Fix credentials for ERXMISC0_EL1 and ERXMISC1_EL1

AARCH64: Fix credentials for ERXMISC0_EL1 and ERXMISC1_EL1

fixes arm-software/tf-issues#620

Signed-off-by: Jan Dabros <jsd@semihalf.com>

backtrace: Introduce backtrace function

This function diplays the backtrace, the current EL and security state
to allow a post-processing tool to choose the right binary to interpret
the dump.

The

backtrace: Introduce backtrace function

This function diplays the backtrace, the current EL and security state
to allow a post-processing tool to choose the right binary to interpret
the dump.

The output can be fed to GNU addr2line to resolve function names given
an ELF binary compiled with debug information. The "-i" flag is
recommended to improve display in case of inlined functions. The *.dump
files generated during the build process can also be used.

The function works in AArch64 and AArch32. In AArch32 it only works in
A32 mode (without T32 interworking), which is enforced in the Makefile.

Sample output of a backtrace at EL3:

BACKTRACE: START: function_name
0: EL3: 0x798
1: EL3: 0x538
2: EL3: 0x550
3: EL3: 0x55c
4: EL3: 0x568
5: EL3: 0x5a8
6: EL3: 0xf4
BACKTRACE: END: function_name

In order to enable it the new option ENABLE_BACKTRACE must be set to 1.
This option is set to 1 by default only in AArch64 debug builds. As
usual, it can be overridden by the platform makefile and in the build
command line.

Change-Id: Icaff39b0e5188329728be2f3c72b868b2368e794
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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libc: Move tf_printf and tf_snprintf to libc

Change their names to printf and snprintf. They are much smaller than
the previous versions we had, which makes them better suited for the
Trusted Firmwa

libc: Move tf_printf and tf_snprintf to libc

Change their names to printf and snprintf. They are much smaller than
the previous versions we had, which makes them better suited for the
Trusted Firmware.

Change-Id: Ia872af91b7b967c47fce012eccecede7873a3daf
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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libc: Fix all includes in codebase

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb03

libc: Fix all includes in codebase

The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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libc: Cleanup SCC headers

Only leave the parts relevant to the Trusted Firmware.

Change-Id: I0444c16e402f6c1629211d03bf6cb32ca3dbcf59
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

libc: Add AArch32 and AArch64 headers

Change-Id: I4f58bb4660078c9bc76d2826c90b2fa711719a3e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

libc: Introduce files from SCC

Taken from http://git.simple-cc.org/scc/ from the following commit:

67508ad14af314cea2229783d3c084f28c41daf0

Permission has been granted from the author to use them

libc: Introduce files from SCC

Taken from http://git.simple-cc.org/scc/ from the following commit:

67508ad14af314cea2229783d3c084f28c41daf0

Permission has been granted from the author to use them under the
license BSD-3-Clause instead of ISC.

Change-Id: I65c0ce3ab60c49d34a57533af12a74bd7bde88e5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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libc: Cleanup FreeBSD files

Remove code specific to FreeBSD so that they can be used in this
repository.

Change-Id: I5c11eb5b3c05a7fb91aed08371a1f7a0e6122a94
Signed-off-by: Antonio Nino Diaz <anton

libc: Cleanup FreeBSD files

Remove code specific to FreeBSD so that they can be used in this
repository.

Change-Id: I5c11eb5b3c05a7fb91aed08371a1f7a0e6122a94
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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