| 99f6790c | 28-Aug-2024 |
Jackson Cooper-Driver <jackson.cooper-driver@arm.com> |
feat(tc): add SLC MSC nodes to TC4 DT
These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.
feat(tc): add SLC MSC nodes to TC4 DT
These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312
show more ...
|
| 8dec6303 | 01-Jul-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(tc): modify ethernet configuration for TC4 FPGA
Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: I7b180c3eb90d7557d0011a25a742106f70
fix(tc): modify ethernet configuration for TC4 FPGA
Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: I7b180c3eb90d7557d0011a25a742106f703cd264
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
|
| 5de9d79b | 01-Jul-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(tc): modify gpio controller base addr for TC4 FPGA
Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
fix(tc): modify gpio controller base addr for TC4 FPGA
Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.
Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
|
| bb9b8936 | 01-Jul-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(tc): modify DPU configuration in dts for TC4 FPGA
TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.
Change-Id: Ie31933e0bcbd4899459358299
fix(tc): modify DPU configuration in dts for TC4 FPGA
TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.
Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
|
| cada6ca3 | 14-Aug-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu
As per GPU team, this change should be helpful to improve
the performance.
Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-b
fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu
As per GPU team, this change should be helpful to improve
the performance.
Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
|
| bf223c79 | 05-Aug-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(tc): fix SMMU streamId for tc4 gpu
Currently used stream id 0x200 gives below fault,
[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000
fix(tc): fix SMMU streamId for tc4 gpu
Currently used stream id 0x200 gives below fault,
[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000000000
[ 9.547393][ C0] raw fault status: 0x400D02C0
[ 9.547393][ C0] exception type 0xC0: TRANSLATION_FAULT at level 0
[ 9.547393][ C0] access type 0x2: READ
As per the GPU team, GPU stream id is 0 on TC4-FPGA so change it.
Change-Id: I3aed62289c5b96fb850f0022ea7f5172c606eb95
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
|
| 6a9e5ffd | 22-Nov-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp2-fdts): add STM32MP257F-DK board support
Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI
feat(stm32mp2-fdts): add STM32MP257F-DK board support
Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LVDS connector ...
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Olivier BIDEAU <olivier.bideau@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I95bb84b00eafce8031f26f7243ecc0fce843d170
show more ...
|
| 575d6dd7 | 09-Oct-2024 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(stm32mp2-fdts): fix SDMMC slew rate
New slew rate applied.
SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.
SDMMC
fix(stm32mp2-fdts): fix SDMMC slew rate
New slew rate applied.
SDMMC:
- for SD card and eMMC:
- clk at 2.
- cmd and data at 1.
- for Wifi
- clk at 1.
- cmd and data at 0.
SDMMC1:
- for dk board:
- clk at 2.
- cmd and data at 1.
- for eval board:
- clk at 3.
- cmd and data at 2.
Change-Id: I2dfa62aca08a613e0532746050246fc8dc476ff8
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
show more ...
|
| 624deb08 | 19-Jun-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
feat(tc): add MCN PMU nodes in dts for TC4
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zey
feat(tc): add MCN PMU nodes in dts for TC4
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251
show more ...
|
| 33573ea6 | 11-Dec-2024 |
Valentin Caron <valentin.caron@foss.st.com> |
fix(stm32mp1-fdts): re-enable RTC clock
On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.
Signed-off-by: Valentin
fix(stm32mp1-fdts): re-enable RTC clock
On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
show more ...
|