feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image

Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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fix(rd1ae): fix rd1-ae device tree

Fix issues in RD1-AE flattened device tree source

- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (wi

fix(rd1ae): fix rd1-ae device tree

Fix issues in RD1-AE flattened device tree source

- Update GIC GICR register region size to 0x40_0000.
GICR region size = 16 (RDcount) * 64KB frame size * 4 (with GIC v4.1)
- Update cpu_on function ID in psci node.
Use SMC64 version function ID 0xc4000003 instead. Although this
property doesn't actually take effect, align its value with
cpu_suspend selection to avoid any confusion.

Change-Id: Ib0840db45d32f0c8f1eb7dc74dc7d9b4ca6de0c3
Signed-off-by: David Hu <david.hu2@arm.com>

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Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for O

Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for OP-TEE SPMC

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feat(rd1ae): add Generic Timer in device tree

Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 40

feat(rd1ae): add Generic Timer in device tree

Add a node for AP_REFCLK Non-Secure Generic Timer in device tree, which
acts as a system timer to fix the failure of SystemReady IR ACS BSA
test case 402.

Refer to https://github.com/ARM-software/bsa-acs/blob/v23.09_REL1.0.6\
/docs/arm_bsa_testcase_checklist.rst?plain=1#L115
for more information.

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Change-Id: I3e63a5ecfd8c6211f917ca3844b8b7bda208d83a

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fix(stm32mp15-fdts): correct MCO2_PLL4 clock name for DHCOM

This clock name was renamed from MCO2_PLL4P to MCO2_PLL4 with the RCC
binding update commit [1]. This file was missed in that update, and

fix(stm32mp15-fdts): correct MCO2_PLL4 clock name for DHCOM

This clock name was renamed from MCO2_PLL4P to MCO2_PLL4 with the RCC
binding update commit [1]. This file was missed in that update, and the
board fails to compile.

[1]: 52b253bfa2 feat(dt-bindings): new RCC DT bindings

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I215abff1fc275ac1ef6dfb2ac86b9223e6990064

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fix(tc): fix the MHUv3 interrupt name in DT

Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.

Signed-off-by: Leo Yan <leo.yan@arm.c

fix(tc): fix the MHUv3 interrupt name in DT

Change the interrupt name "combined-mbx" to "combined", which is the
correct naming defined in the mainline kernel.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I8d2da2dd0e9dac2bed3963efc695a277bb5e14bd

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feat(stm32mp2): add BL31 device tree support

BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in

feat(stm32mp2): add BL31 device tree support

BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in DDR, in a
spare area.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I320a05859e1aa3dd8db9a274e7201075a8c250c2

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Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

* changes:
feat(tc): move flash device to own node
feat(tc): remove static memory used for fwu
fix(tc): correct NS timer frame ID f

Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

* changes:
feat(tc): move flash device to own node
feat(tc): remove static memory used for fwu
fix(tc): correct NS timer frame ID for TC

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feat(stm32mp2-fdts): update STM32MP257F-EV1 DT

Add include for DDR configuration, and reference to OTP storing the
board ID.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf

feat(stm32mp2-fdts): update STM32MP257F-EV1 DT

Add include for DDR configuration, and reference to OTP storing the
board ID.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie2d5272ecf1dac77b91b2c148ec4dc1fb7b76631

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feat(fdts): add DDR4 files for STM32MP2

These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.ga

feat(fdts): add DDR4 files for STM32MP2

These DT files will be used by STM32MP2 boards. They embed DDR parameters
for DDR4 2x8Gb 2*16bits, at 800MHz or 1200MHz.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iec73f9c5028f897624125082bdb591274aad3afc

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feat(stm32mp25-fdts): add DDRCTRL and DDRPHY settings in DDR node

Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed prop

feat(stm32mp25-fdts): add DDRCTRL and DDRPHY settings in DDR node

Complete DDR node with all necessary DDRCTRL (register values) and
DDRPHY (user input values) settings.
Add also name and speed properties.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ie63f48dcacefe590c68cf6ec694d9e82349cece8

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feat(stm32mp25-fdts): add DDR power supplies

Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.

Signed-off-by: Patrick Delaunay <patrick.delaunay@

feat(stm32mp25-fdts): add DDR power supplies

Add the required power supplies for DDR nodes. The power supplies are
provided by STPMIC2 regulators.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I951da75a554bc4fbfbc69ea9cd1171d99ed7ce46

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feat(stm32mp2-fdts): add memory node

Add ddr node in stm32mp251.dtsi file, which gives addresses to DDR PHY
and DDR controller.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I719bfd1

feat(stm32mp2-fdts): add memory node

Add ddr node in stm32mp251.dtsi file, which gives addresses to DDR PHY
and DDR controller.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I719bfd1640a8217ff79e79b5b53845b75421d298

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feat(tc): remove static memory used for fwu

With the updated firmware update implementation in the Trusted Services,
it is no longer needed to carve out static memory. Memory will be
allocated dynam

feat(tc): remove static memory used for fwu

With the updated firmware update implementation in the Trusted Services,
it is no longer needed to carve out static memory. Memory will be
allocated dynamically in U-Boot and shared with the firmware update
secure partition of Trusted Services.

Change-Id: I0fb128a458773236ee10526edfa1116b229e4d6e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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feat(rd1ae): add device tree files

This commit Add FW_CONFIG and HW_CONFIG device trees

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: Ia6cbf06def8ec9b74ef9040bab801278a3117899

feat(arm): add support for loading CONFIG from BL2

This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_conf

feat(arm): add support for loading CONFIG from BL2

This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_config` device tree when resetting to the BL2 scenario.

Additionally, the FW_CONFIG image reference has been added to the
fdts/tbbr_cot_descriptors.dtsi file in order to use in the scenario of
RESET_TO_BL2.

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I11de497b7dbb1386ed84d939d6fd2a11856e9e1b

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feat(stm32mp2-fdts): describe stpmic2 power supplies

Describe PMIC power supplies in STM32MP257F-EV1 board DT file.

Change-Id: I14df5d210909d95b2164197eb910a9ea0aa0b51d
Signed-off-by: Pascal Paille

feat(stm32mp2-fdts): describe stpmic2 power supplies

Describe PMIC power supplies in STM32MP257F-EV1 board DT file.

Change-Id: I14df5d210909d95b2164197eb910a9ea0aa0b51d
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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feat(stm32mp2-fdts): add I2C7 pin muxing

It will be used for PMIC on STM32MP257F-EV board.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7f95220512de4416323b381fec7c7dcb044c64fd

feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2

Update stm32mp251.dtsi SoC DT file to include UART and I2C nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxi

feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2

Update stm32mp251.dtsi SoC DT file to include UART and I2C nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I6f52ec2c1735d28ba4a424af71e7eae5b0ac3e0d

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feat(stm32mp2): manage DDR FW via FIP

This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.

DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the

feat(stm32mp2): manage DDR FW via FIP

This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.

DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the SRAM1 will be allocated to TF-A.
RISAB3 has to be configured to allow access to SRAM1.
Add image ID and update maximum number on platform side also.

Fill related descriptor information, add policy and update numbers.
DDR_TYPE variable is used to identify binary file, and image is now
added in the fiptool command line.

The DDR PHY firmware is not in TF-A repository. It can be found at
https://github.com/STMicroelectronics/stm32-ddr-phy-binary
To ease the selection of the firmware path, STM32MP_DDR_FW_PATH is added
to platform.mk file.

Change-Id: I09ab0a5c63406055a7b5ccd16d65e443de47ca2f
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2-fdts): add BL31 info in fw-config

Add BL31 load address (beginning on SYSRAM) and size in fw-config DT
file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Mé

feat(stm32mp2-fdts): add BL31 info in fw-config

Add BL31 load address (beginning on SYSRAM) and size in fw-config DT
file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I2fcd8d326f394090401ac59b47216d59d3e911bc

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feat(tc): bind DPU SMMU on TC4

TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is
used as the DPU SMMU instead of the existing SMMU used for both the GPU
and DPU. Update the devi

feat(tc): bind DPU SMMU on TC4

TC4 adds a new SMMU-700 specifically for the DPU (in the RoS). This is
used as the DPU SMMU instead of the existing SMMU used for both the GPU
and DPU. Update the devicetree to reflect this.

Note that the streamID values have also changes for this new SMMU. This
is because TC4 also updates the new SMMU to use a different streamID for
each DPU port - these must all be added to the device tree.

Change-Id: If2ce9749e40937fd1291346d071b691cfb662f2e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): bind GPU SMMU on TC4

A SMMU-700 is used on TC4 for only GPU, on both FVP and FPGA. Add DT
binding for it.

Change-Id: I1b840676fd02c3961d4efdd769f12a4b01d459fb
Signed-off-by: Leo Yan <leo.

feat(tc): bind GPU SMMU on TC4

A SMMU-700 is used on TC4 for only GPU, on both FVP and FPGA. Add DT
binding for it.

Change-Id: I1b840676fd02c3961d4efdd769f12a4b01d459fb
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): update DT for Drage GPU

This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC p

feat(tc): update DT for Drage GPU

This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.

Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3

feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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