corstone700: set UART clocks to 32MHz

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banav

corstone700: set UART clocks to 32MHz

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Fix topology description of cpus for DynamIQ based FVP

DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for Dynam

Fix topology description of cpus for DynamIQ based FVP

DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.

Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "Replace dts includes with C preprocessor syntax" into integration

fdts: stm32mp1: remove second QSPI flash instance

Remove second flash node as only one must be used
by QSPI NOR driver.

Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5
Signed-off-by: Lionel De

fdts: stm32mp1: remove second QSPI flash instance

Remove second flash node as only one must be used
by QSPI NOR driver.

Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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fdts: stm32mp1: update for FMC2 pin muxing

Include the required FMC2 pinmux definition for the
NAND management.

Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591
Signed-off-by: Lionel Debieve <l

fdts: stm32mp1: update for FMC2 pin muxing

Include the required FMC2 pinmux definition for the
NAND management.

Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Replace dts includes with C preprocessor syntax

Using the /include/ syntax, the include was evaluated by dtc, only after running
the preprocessor, therefore the .dtsi files were not preprocessed. Th

Replace dts includes with C preprocessor syntax

Using the /include/ syntax, the include was evaluated by dtc, only after running
the preprocessor, therefore the .dtsi files were not preprocessed. This patch
adds the #include syntax instead. Evaluating this and preprocessing the files
now happens in a single step, done by the C preprocessor.

Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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A5DS: Correct system freq, Cache Writeback Granule

Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeb

A5DS: Correct system freq, Cache Writeback Granule

Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback

Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

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fdts: a5ds: cleanup enable-method in devicetree

Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.

Change-Id: I9b5728

fdts: a5ds: cleanup enable-method in devicetree

Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.

Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

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fdts: a5ds: add L2 cache node in devicetree

This change is to add L2 cache node into a5ds device tree.

Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.ba

fdts: a5ds: add L2 cache node in devicetree

This change is to add L2 cache node into a5ds device tree.

Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

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Add multithreaded DynamIQ dts file

The new dts file overrides the MPIDR values of the processing elements
which were defined in the common dtsi file. The new dts file defines
four cores in a single

Add multithreaded DynamIQ dts file

The new dts file overrides the MPIDR values of the processing elements
which were defined in the common dtsi file. The new dts file defines
four cores in a single cluster, each core having two threads.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I0f8d8d250289077aee11eede4508871bb61dbc88

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fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe an

fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58

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Merge changes from topic "ld/stm32-authentication" into integration

* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
c

Merge changes from topic "ld/stm32-authentication" into integration

* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
crypto: stm32_hash: Add HASH driver

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a5ds: add multicore support

Enable cores 1-3 using psci. On receiving the smc call from kernel,
core 0 will bring the secondary cores out pen and signal an event for
the cores. Currently on switchin

a5ds: add multicore support

Enable cores 1-3 using psci. On receiving the smc call from kernel,
core 0 will bring the secondary cores out pen and signal an event for
the cores. Currently on switching the cores is enabled i.e. it is not
possible to suspend, switch cores off, etc.

Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f
Signed-off-by: Usama Arif <usama.arif@arm.com>

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stm32mp1: add authentication support for stm32image

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates

stm32mp1: add authentication support for stm32image

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51

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Add Linux DTS files for 32 bit threaded FVPs

RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file co

Add Linux DTS files for 32 bit threaded FVPs

RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file containing the shifted affinity values.

Beside these values the DTS files should be the same so the common part
was moved into a new file which is included in the DTS files with
shifted and non-shifted affinities.

The same setup already exists for 64 bit systems.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d

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plat/arm: Introduce corstone700 platform.

This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
Thi

plat/arm: Introduce corstone700 platform.

This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.

Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.

It is an initial port and additional features are expected to be added
later.

Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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plat/arm: Introduce A5 DesignStart platform.

This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.

Currently with

plat/arm: Introduce A5 DesignStart platform.

This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.

Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab

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fdts: stm32mp1: realign device tree files with internal devs

Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB re

fdts: stm32mp1: realign device tree files with internal devs

Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB regulator.
Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
Update DTSI file for SDMMC compatible, but overwrite it with the former
name.
Move BSEC board_id node to boards DTS files, as this OTP is specific to
STMicroelectronics boards.

Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add general SYSCFG management

The system configuration controller is mainly used to manage
the compensation cell and other IOs and system related settings.

The SYSCFG driver is in charge

stm32mp1: add general SYSCFG management

The system configuration controller is mainly used to manage
the compensation cell and other IOs and system related settings.

The SYSCFG driver is in charge of configuring masters on the interconnect,
IO compensation, low voltage boards, or pull-ups for boot pins.
All other configurations should be handled in Linux drivers requiring it.

Device tree files are also updated to manage vdd-supply regulator.

Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fdts: Fix DTC warnings for STM32MP1 platform

DTC issues below warnings for STM32MP1 platform for using upper case
in unit address:

fdts/stm32mp15-ddr.dtsi:8.20-151.5: Warning (simple_bus_reg): /soc

fdts: Fix DTC warnings for STM32MP1 platform

DTC issues below warnings for STM32MP1 platform for using upper case
in unit address:

fdts/stm32mp15-ddr.dtsi:8.20-151.5: Warning (simple_bus_reg): /soc/ddr@5A003000: simple-bus unit address format error, expected "5a003000"
fdts/stm32mp157c-security.dtsi:9.25-13.5: Warning (simple_bus_reg): /soc/stgen@5C008000: simple-bus unit address format error, expected "5c008000"

Fix this by using the lower case unit address for concerned nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Id3d19ac3b47ec6bcea2bd3382225e2e923dc4a70

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stm32mp1: Add Avenger96 board support

Add board support for Avenger96 board from Arrow Electronics. This
board is based on STM32MP157A SoC and is one of the 96Boards Consumer
Edition platform.

More

stm32mp1: Add Avenger96 board support

Add board support for Avenger96 board from Arrow Electronics. This
board is based on STM32MP157A SoC and is one of the 96Boards Consumer
Edition platform.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/avenger96/

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Ic905f26c38d03883c6e4ea221b4b275a4b534857

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fdts: stm32mp1: add bsec node

This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status

fdts: stm32mp1: add bsec node

This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status and secure-status, as these OTPs are accessible
by secure and non-secure world.

The stgen node is also moved to this file.

Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge pull request #1836 from Yann-lms/docs_and_m4

Update documentation for STM32MP1 and add Cortex-M4 support

stm32mp1: add minimal support for co-processor Cortex-M4

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minima

stm32mp1: add minimal support for co-processor Cortex-M4

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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plat/arm: Support for Cortex A5 in FVP Versatile Express platform

Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex

plat/arm: Support for Cortex A5 in FVP Versatile Express platform

Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.

Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>

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