| b48883c7 | 03-Aug-2020 |
Andre Przywara <andre.przywara@arm.com> |
arm_fpga: Add devicetree file
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to suppor
arm_fpga: Add devicetree file
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.
Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.
Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| e1cbcf96 | 31-Jul-2020 |
Manoj Kumar <manoj.kumar3@arm.com> |
fdts: add device tree sources for morello platform
Change-Id: Ib5945c37983505f327a195bdb8b91ed1b7b90921
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> |
| 277d6af5 | 18-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU a
fdts: stm32mp1: realign device tree with kernel
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 8f734c65 | 18-Aug-2020 |
Usama Arif <usama.arif@arm.com> |
fdts: tc0: update MHUv2 interrupt number
This is as part of the architecture change in TC0.
Change-Id: I470241f67938e7998941d26f0e8bc05073234152
Signed-off-by: Usama Arif <usama.arif@arm.com> |
| 35d626bb | 31-Jul-2020 |
Sayanta Pattanayak <sayanta.pattanayak@arm.com> |
n1sdp: add support for remote chip pcie.
Remote chip ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.
Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sa
n1sdp: add support for remote chip pcie.
Remote chip ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.
Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
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|
| a6f65b11 | 15-Sep-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fdts: corstone700: add NXP isp1763 node to device tree" into integration |
| 0dc52294 | 22-Jul-2020 |
Avinash Mehta <avinash.mehta@arm.com> |
Enabling DPU in dts file for TC0
This change replaces hdlcd with DPU in dts file for TC0
Change-Id: If25dfd3ddffc07279ab487f65e1bb82b27a26604
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> |
| 23875c3f | 15-Jul-2020 |
Rui Miguel Silva <rui.silva@linaro.org> |
fdts: corstone700: add NXP isp1763 node to device tree
Add USB IP node as the MPS3 board has the NXP isp1763 host controller.
Change-Id: I47c57e4c8345d244c46895b52fcaecc1c6f1b504
Signed-off-by: Rui
fdts: corstone700: add NXP isp1763 node to device tree
Add USB IP node as the MPS3 board has the NXP isp1763 host controller.
Change-Id: I47c57e4c8345d244c46895b52fcaecc1c6f1b504
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
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|
| ee99356b | 02-Sep-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "dtsi: Update the nv-counter node in the device tree" into integration |
| 699d8a12 | 23-Aug-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
dtsi: Update the nv-counter node in the device tree
Created a header file defining the id of the various nv-counters
used in the system.
Also, updated the device tree to add 'id' property for the tr
dtsi: Update the nv-counter node in the device tree
Created a header file defining the id of the various nv-counters
used in the system.
Also, updated the device tree to add 'id' property for the trusted
and non-trusted nv-counters.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia41a557f7e56ad4ed536aee11c7a59e078ae07c0
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|
| 8ea4f80a | 12-Aug-2020 |
Usama Arif <usama.arif@arm.com> |
fdts: tc0: add support for cpu-idle-states
This includes both cpu and cluster sleep parameters.
Change-Id: I6a9e90b88508d6d2acd2538007cbbdd1cf976442
Signed-off-by: Usama Arif <usama.arif@arm.com> |
| a41973a9 | 10-Jun-2020 |
Usama Arif <usama.arif@arm.com> |
fdts: tc0: Add node for mmc
The pl180 mmc uses 3.3V fixed regulator and vexpress
sysreg for card detection and write protect.
Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff
Signed-off-by: Usa
fdts: tc0: Add node for mmc
The pl180 mmc uses 3.3V fixed regulator and vexpress
sysreg for card detection and write protect.
Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff
Signed-off-by: Usama Arif <usama.arif@arm.com>
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|
| 070632f9 | 04-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "SPM: build OP-TEE as an S-EL1 Secure Partition" into integration |
| 03a5225c | 23-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
tbbr/dualroot: rename SP package certificate file
Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.
SP_CONTENT_
tbbr/dualroot: rename SP package certificate file
Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.
SP_CONTENT_CERT_ID is the certificate file which is currently generated
and signed with trusted world key which in-turn is derived from Silicon
provider RoT key.
To allow dual signing domain for SP packages, other certificate file
will be derived from Platform owned RoT key.
This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
does other related changes.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
show more ...
|
| db1ef41a | 01-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPM: build OP-TEE as an S-EL1 Secure Partition
Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.
Increase ARM_SP_MAX_SIZE to cope with
SPM: build OP-TEE as an S-EL1 Secure Partition
Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.
Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
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|
| 000653b4 | 06-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
fdts: n1sdp: DTS file for single-chip and multi-chip environment.
N1SDP supports both single-chip and multi-chip environment.
Added DTS file for both type of environment.
Enabled DTS files compilat
fdts: n1sdp: DTS file for single-chip and multi-chip environment.
N1SDP supports both single-chip and multi-chip environment.
Added DTS file for both type of environment.
Enabled DTS files compilation for N1SDP platform.
Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0
Co-authored-by: Robin Murphy <Robin.Murphy@arm.com>
Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com>
Co-authored-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
show more ...
|
| 567bfe51 | 29-Jun-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
dts: Add CoT descriptor nodes and properties in device tree
Added CoT descriptor nodes and properties in device tree.
Currently, CoT descriptors which are used by BL2 are added as part
of device tre
dts: Add CoT descriptor nodes and properties in device tree
Added CoT descriptor nodes and properties in device tree.
Currently, CoT descriptors which are used by BL2 are added as part
of device tree.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0
show more ...
|
| ef93cfa3 | 06-Jul-2020 |
Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
corstone700: splitting the platform support into FVP and FPGA
This patch performs the following:
- Creating two corstone700 platforms under corstone700 board:
fvp and fpga
- Since the FVP and F
corstone700: splitting the platform support into FVP and FPGA
This patch performs the following:
- Creating two corstone700 platforms under corstone700 board:
fvp and fpga
- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
- Enabling NEED_BL33 option
- Fixing non-secure image base: For no preloaded bl33 we want to
have the NS base set on shared ram. Setup a memory map region
for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY
Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
show more ...
|
| 452d5e5e | 02-Jun-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime.
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime. This
feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.
Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| bca652a2 | 03-Jun-2020 |
Etienne Carriere <etienne.carriere@st.com> |
dts: stm32mp157c: fix etzpc node location in DTSI file
Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded wh
dts: stm32mp157c: fix etzpc node location in DTSI file
Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded while
rebasing.
Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d
Fixes: 627298d4b655 ("dts: stm32mp157c: add etzpc node")
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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|
| 627298d4 | 08-Dec-2019 |
Etienne Carriere <etienne.carriere@st.com> |
dts: stm32mp157c: add etzpc node
Add a node for the ETZPC device so that driver initializes during
stm32mp15* boot sequence.
Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f
Signed-off-by: Etie
dts: stm32mp157c: add etzpc node
Add a node for the ETZPC device so that driver initializes during
stm32mp15* boot sequence.
Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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|
| f5c58af6 | 17-Apr-2020 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce TC0 platform
This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.
TC0 has a SCP which brings t
plat/arm: Introduce TC0 platform
This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.
TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.
Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.
Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>
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|
| 003faaa5 | 13-May-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
FVP: Add support for passing platform's topology to DTS
This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correc
FVP: Add support for passing platform's topology to DTS
This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.
Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| cbf9e84a | 18-Dec-2019 |
Balint Dobszay <balint.dobszay@arm.com> |
plat/arm/fvp: Support performing SDEI platform setup in runtime
This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead
plat/arm/fvp: Support performing SDEI platform setup in runtime
This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.
Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| e3c152d1 | 17-Apr-2020 |
lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com> |
fdts: a5ds: Fix for the system timer issue.
A5DS FPGA system timer clock frequency is 7.5Mhz.
The dt is file updated inline with the hardware
clock frequency.
Change-Id: I3f6c2e0d4a7b293175a42cf398
fdts: a5ds: Fix for the system timer issue.
A5DS FPGA system timer clock frequency is 7.5Mhz.
The dt is file updated inline with the hardware
clock frequency.
Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9
Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
show more ...
|