fix(morello): dts: use documented DPU compatible string

The official Arm Komeda DPU DT binding only mentions the "arm,mali-d71"
string as a possible compatible string. The D32 version is just a
vari

fix(morello): dts: use documented DPU compatible string

The official Arm Komeda DPU DT binding only mentions the "arm,mali-d71"
string as a possible compatible string. The D32 version is just a
variant of the D71, and the revision can and will be auto-detected at
runtime.
Add the usual fallback compatible string scheme to contain a documented
compatible string.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ic1eade122b030dc983944b161eec175facf75357

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fix(morello): dts: fix DP SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2

fix(morello): dts: fix DP SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2ce00000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============

Swap the order of the interrupts to improve bindings compliance.

Actually in this case the binding needs to be extended, since PRI is not
implemented in the SMMU in this case, so the PRI IRQ should be optional,
but we still want to describe the CMDQ sync IRQ. A patch for the binding
is pending.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I3978f1c087136cd4c2e8f7fd4d1bba5b95f72726

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fix(morello): dts: fix SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@4f40

fix(morello): dts: fix SMMU IRQ ordering

The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@4f400000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'priq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============

Swap the order of the interrupt-names and their corresponding interrupts
values to improve bindings compliance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I2110b8509593a4f1aadff11bd518ec4a0f3f5d3c

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fix(morello): dts: add model names

The core root node DT bindings require every DT to have a "model"
property. Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: /: 'model' is a

fix(morello): dts: add model names

The core root node DT bindings require every DT to have a "model"
property. Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: /: 'model' is a required property
From schema: dt-schema.git/dtschema/schemas/root-node.yaml
============

Add a model name to both the SoC and FVP files to improve bindings
compliance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I64923edb947f8939dfa24c13a37996b1ba34ea54

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refactor(stm32mp1-fdts): add missing spaces for consistent codestyle

Change-Id: Ie650728a0c671f553679b050afd969ce604ca111
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

refactor(stm32mp1-fdts): drop unused DDR calibration result on DHCOM

Change-Id: Ie2736ef4c463c51d109c13e59f541fe65039d7c6
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board

This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for sho

feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board

This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for short). The SoM features an
STM32MP157C SoC with 1 GB DDR3, 8 GB eMMC, microSD and 2 MB SPI flash.
The baseboard has multiple UART, USB, SPI, and I2C ports/headers and several
other interfaces that are not important for TF-A.

These dts(i) files are based on DHCOM dt's from Linux 5.16 and U-Boot 2022.01.
The DRAM calibration values are taken from U-Boot 2022.01 and are optimized for
industrial temperature range above 85° C.

TF-A on this board was fully tested with the latest OP-TEE developer setup.

Change-Id: I696c01742954d761fbad312cd1059e3ab01fa93c
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

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feat(stm32mp15): manage OP-TEE shared memory

On STM32MP15, there is currently an OP-TEE shared memory area at the end
of the DDR. But this area will in term be removed. To allow a smooth
transition,

feat(stm32mp15): manage OP-TEE shared memory

On STM32MP15, there is currently an OP-TEE shared memory area at the end
of the DDR. But this area will in term be removed. To allow a smooth
transition, a new flag is added (STM32MP15_OPTEE_RSV_SHM). It reflects
the OP-TEE flag: CFG_CORE_RESERVED_SHM. The flag is enabled by default
(no behavior change). It will be set to 0 when OP-TEE is aligned, and
then later be removed.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I91146cd8a26a24be22143c212362294c1e880264

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feat(stm32mp1-fdts): change pin-controller to pinctrl

Due to commit updating kernel yaml file [1], we need to align TF-A DT
files to what is done in kernel.

[1] c09acbc499e8 ("dt-bindings: pinctrl:

feat(stm32mp1-fdts): change pin-controller to pinctrl

Due to commit updating kernel yaml file [1], we need to align TF-A DT
files to what is done in kernel.

[1] c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml")

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Id717162e42d3959339d6c01883e87a9d4399f5d9

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fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver

With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:

NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux

fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver

With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:

NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux Automation MC-1 board
ERROR: regul ldo3: max value 750 is invalid
PANIC at PC : 0x2ffeebb7

as the driver takes great offense at the content of the device
tree. The parts in question were copy-pasted from ST DTs, but
those ST DTs were fixed by commit 67d95409baae
("refactor(stm32mp1-fdts): update regulator description").

Fix the breakage by transplanting the same changes into all
remaining STM32MP1 DTs.

Change was boot-tested on MC-1, but only build tested for the
other two.

Fixes: bba9fdee589f ("feat(stm32mp1): add regulator framework compilation")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: I143d0091625f62c313b3b71449c9ad99583d01c8

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fix(stm32mp1-fdts): correct memory mapping for STM32MP13

On STM32MP13, OP-TEE will be loaded at the beginning of the secure
memory, and will be responsible for its shared memory.
The memory allocate

fix(stm32mp1-fdts): correct memory mapping for STM32MP13

On STM32MP13, OP-TEE will be loaded at the beginning of the secure
memory, and will be responsible for its shared memory.
The memory allocated to OP-TEE is then 32MB, and the shared memory
does no more appear in the STM32MP13 fw-config DT file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e9238ddb4d82079b9ddf8fc8f6916b5b989d263

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feat(tc): enable CI-700 PMU for profiling

Change-Id: Iaafdfc440b362022e6103eabf3fb2ebed85b6575
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>

refactor(stm32mp1-fdts): remove nvmem_layout node

Remove the nvmem_layout node with compatible "st,stm32-nvmem-layout"
no more used in TF-A code to simplify the device tree.

Signed-off-by: Patrick

refactor(stm32mp1-fdts): remove nvmem_layout node

Remove the nvmem_layout node with compatible "st,stm32-nvmem-layout"
no more used in TF-A code to simplify the device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3748b20b7d3c60ee64ead15541fac1fd12656600

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fix(morello): dts: fix stdout-path target

According to the DT spec, stdout-path must either start with the full
path to a node, or with an alias.
"soc_uart0" is neither of them, and consequently the

fix(morello): dts: fix stdout-path target

According to the DT spec, stdout-path must either start with the full
path to a node, or with an alias.
"soc_uart0" is neither of them, and consequently the Linux kernel
complains that it cannot find the root console device when just given
"earlycon" on the kernel command line:
===========
[ 0.000000] OF: fdt: earlycon: stdout-path soc_uart0 not found
===========

Use the already defined "serial0" alias to fix this and make "earlycon"
work in Linux.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie0ddb1909160c930af3831246f0140363bc0b5db

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feat(stm32mp1-fdts): add support for STM32MP13 DK board

This stm32mp135f-dk board embeds a STM32MP135F SoC (900MHz / crypto
capabilities) and following peripherals: STPMIC (power delivery), 512MB
DD

feat(stm32mp1-fdts): add support for STM32MP13 DK board

This stm32mp135f-dk board embeds a STM32MP135F SoC (900MHz / crypto
capabilities) and following peripherals: STPMIC (power delivery), 512MB
DDR3L memory, SDcard, dual RMII Ethernet, display H7, RPI connector,
wifi/BT murata combo, USBOTG/STM32G0/TypeC, STMIPID02/CSI OV5640.
Add board DT file taken from kernel.
Add fw-config files for this new board.

Change-Id: I7cce1f8eb39815d7d1df79311bd7ad41061524b8
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): add DDR support for STM32MP13

Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.co

feat(stm32mp1-fdts): add DDR support for STM32MP13

Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3

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feat(stm32mp1-fdts): add st-io_policies node for STM32MP13

To be able to load images with FIP and FCONF on STM32MP13,
the st-io_policies has to be filled.
It is a copy of the node in stm32mp15_bl2.d

feat(stm32mp1-fdts): add st-io_policies node for STM32MP13

To be able to load images with FIP and FCONF on STM32MP13,
the st-io_policies has to be filled.
It is a copy of the node in stm32mp15_bl2.dtsi .

Change-Id: Ia15f50d1179e9b8aefe621dc5e0070ea845d6aac
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): updates for STM32MP13 device tree compilation

Add stm32mp13_bl2.dtsi files.
Update compilation variables for STM32MP13.

Change-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c
Signed-o

feat(stm32mp1): updates for STM32MP13 device tree compilation

Add stm32mp13_bl2.dtsi files.
Update compilation variables for STM32MP13.

Change-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): add DT files for STM32MP13

STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on So

feat(stm32mp1-fdts): add DT files for STM32MP13

STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on SoC version. Each peripheral node is created.
Some are left empty for the moment , and will be filled later on.

Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes I5d7e3cf3,Ie81f2fc5,If869ac93,I2cf2badf,Ic291eb13 into integration

* changes:
fix(sptool): add leading zeroes in UUID conversion
feat(tc): enable SMMU for DPU
feat(tc): add reser

Merge changes I5d7e3cf3,Ie81f2fc5,If869ac93,I2cf2badf,Ic291eb13 into integration

* changes:
fix(sptool): add leading zeroes in UUID conversion
feat(tc): enable SMMU for DPU
feat(tc): add reserved memory region for Gralloc
feat(tc): enable GPU
fix(tc): remove the bootargs node

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feat(tc): enable SMMU for DPU

The SMMU needs to be enabled to support 8GB RAM

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ie81f2fc59886c52e9d6ed799ea73f49eb7a7c307

feat(tc): add reserved memory region for Gralloc

Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations

Signed-off-by: Anders Dellien <anders.dellien@arm.com>

feat(tc): add reserved memory region for Gralloc

Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: If869ac930fadc374ec435cae3847ba374584275b

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feat(tc): enable GPU

Add DTS node for GPU to support hardware rendering in Android

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I2cf2badf5b15e59a910f6cf7d3d30fdfaf4fe9ce

fix(tc): remove the bootargs node

We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b30

fix(tc): remove the bootargs node

We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b307f10354c2c2797c6fc9b053e83

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feat(stm32mp1-fdts): update NVMEM nodes

Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address a

feat(stm32mp1-fdts): update NVMEM nodes

Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.
Most of these were already done but it was missing for ED1 board.

Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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