fix(fvp): fdts: fix memtimer subframe addressing

The arm,armv7-timer-mem DT binding documentation demands that the
#size-cells property should be <1> only.

Adjust the value to be <1> and drop the

fix(fvp): fdts: fix memtimer subframe addressing

The arm,armv7-timer-mem DT binding documentation demands that the
#size-cells property should be <1> only.

Adjust the value to be <1> and drop the now needless leading 0 in the
frame's reg property. Convert to #address-cell = <1> on the way.
Also adjust the interrupts property to use the proper GIC macros.

Change-Id: Ia2224663b1e6aaa7cf94af777473641de6a840d2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel

The existing DT files for the base FVP model are having some issues,
that lead to warnings reported by the device tree compiler.

Those

feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel

The existing DT files for the base FVP model are having some issues,
that lead to warnings reported by the device tree compiler.

Those (and many other issues around (updated) DT binding compliance)
were fixed in the Linux kernel tree, so let's sync those files back into
TF-A.
We cannot copy the files "as is" for now, since we rely on certain custom
properties to be added (max-pwr-lvl in the PSCI node, SDEI nodes, etc).

Merge in the changed parts of the Linux kernel DT (from Linux v6.0-rc1),
and rework the base file to allow including the motherboard.dtsi
unchanged. This should make any future update less painful.

As this also affects the FVP VE boards (Cortex-A7 and Cortex-A5), since
they share the motherboard include file, fix them up as well.

Change-Id: I4f74d05e5583747f8849e32f246f74aeec7a9c60
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(fvp): fdts: consolidate GICv2 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally ju

refactor(fvp): fdts: consolidate GICv2 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally just
the interrupt controller node that is different.
Since the GICv3 versions now use a generic DT include file (without any
GIC node), let's reuse that for the GICv2 versions of the FVP as well.
We just add a separate fvp-base-gicv2.dtsi file which describes the
GICv2 interrupt controller. Also shorten the compatible string, since
the GICv2 binding documentation does not allow the current combination.

This allows to remove the mostly redundant nodes from the GICv2 .dts
file.

Change-Id: I9018031bb611fb00ca7dbefc1bff7d40c3f05819
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(fvp): fdts: consolidate GICv3 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally ju

refactor(fvp): fdts: consolidate GICv3 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally just
the interrupt controller node that is different.
To facilitate a unification, refactor the DT include files to explicitly
include a snippet with just the GICv3 description, and a generic base DT
file for the rest. This generic file can then be reused by the GICv2
versions later.

Since we can only have a /memreserve/ entry *before* any DT nodes, move
that line to each file, to allow including the GIC DT file separately.

Change-Id: I9ff357d3fe0ce46e280c30131aeae97a99631512
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): dts: drop 32-bit .dts files

Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and

feat(fvp): dts: drop 32-bit .dts files

Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and aarch64 does not make sense and is not needed.

Probably due to historic reasons (a Linux bug fixed in 2016 with Linux
commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a
different size between aarch64 and aarch32, even though the size of it
is solely governed by the parent's #address-cells property.

Consolidate this to be always 2, and always use two cells to describe
the CPU's MPIDR register.

This removes the last difference of the -aarch32 versions of the FVP
DT files, so just remove all of them. The respective versions without
that suffix can now be used with AArch32 DT clients as well.

Also remove the respective part in the documentation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e

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refactor(fvp): fdts: merge motherboard .dtsi files

For no real reason we were shipping two separate DT include files for the
base FVP motherboard peripherals, one for aarch32, one for aarch64.
There

refactor(fvp): fdts: merge motherboard .dtsi files

For no real reason we were shipping two separate DT include files for the
base FVP motherboard peripherals, one for aarch32, one for aarch64.
There is no difference in the hardware description when using a
different instruction set, and the diff between the two files was about
a missing interrupt map for the 64-bit DT files.

Consolidate the situation by just using a single motherboard .dtsi file,
which relies on an interrupt map by the including files.
Provide that map in the two files where it was missing before, and
change the filenames to let all users include the same file now.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I19b77ecc8da9b4bfbd61d02f910b9ab05dbf92e9

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refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs

The DT files for the Cortex-A5 and Cortex-A7 FVP models include the
shared rtsm_ve-motherboard.dtsi file, which we need to sync with the
up

refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs

The DT files for the Cortex-A5 and Cortex-A7 FVP models include the
shared rtsm_ve-motherboard.dtsi file, which we need to sync with the
upstream Linux version soon.

To prepare for its changed structure there, adjust the top-level
#address-cells and #size-cells properties to be compatible with the
expectations of the Linux version.
Also extend the interrupt map to cover all peripherals listed in the
motherboard file, and use the proper GIC macros to make them more
readable on the way.

Change-Id: I7d1493f1a200e8350530f912833f9ffcc5f94b21
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(fvp): fdts: unify and fix PSCI nodes

The PSCI DT nodes used for the various fvp-base model variants provide
explicit function IDs, as required for the pre-v0.2 PSCI specification.
This prevents

fix(fvp): fdts: unify and fix PSCI nodes

The PSCI DT nodes used for the various fvp-base model variants provide
explicit function IDs, as required for the pre-v0.2 PSCI specification.
This prevents them from being used from both AArch32 and AArch64 DT
clients, and using this version of the PSCI spec is long deprecated
anyway.

Remove the old compatible string and the function properties, to
force clients to use the standard function IDs as described in the PSCI
spec. sys_poweroff and sys_reset were never standardised or used anyway.

There should be no client software around that cannot deal with PSCI
v0.2.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie87deb9898eae79b7307c15bcefcd4b311d4dc22

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fix(stm32mp13-fdts): correct PLL nodes name

Align aliases and node names for PLL nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I863995eb884fc61c10d512bed0fd404b75ead353

feat(ethos-n)!: add support for SMMU streams

The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these

feat(ethos-n)!: add support for SMMU streams

The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.

To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.

The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277

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fix(tc): resolve the static-checks errors

Converted the space indentation to tabs to fix the
errors listed under tf-static-checks CI job.

Change-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068
Signed

fix(tc): resolve the static-checks errors

Converted the space indentation to tabs to fix the
errors listed under tf-static-checks CI job.

Change-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge "feat(tc): add RTC PL031 device tree node" into integration

feat(tc): add RTC PL031 device tree node

It enables RTC PL031 driver in kernel.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: I6d7c1a5b6ce11b3d594f7575a747e72826c8d9b8

Merge changes from topic "morello-dt-fix" into integration

* changes:
fix(morello): dts: remove #a-c and #s-c from memory node
fix(morello): dts: fix GICv3 compatible string
fix(morello): dts:

Merge changes from topic "morello-dt-fix" into integration

* changes:
fix(morello): dts: remove #a-c and #s-c from memory node
fix(morello): dts: fix GICv3 compatible string
fix(morello): dts: fix DT node naming
fix(morello): dts: fix SCMI shmem/mboxes grouping
fix(morello): dts: use documented DPU compatible string
fix(morello): dts: fix DP SMMU IRQ ordering
fix(morello): dts: fix SMMU IRQ ordering
fix(morello): dts: add model names
fix(morello): dts: fix stdout-path target

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Merge changes from topic "stm32mp15-dt-updates" into integration

* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refa

Merge changes from topic "stm32mp15-dt-updates" into integration

* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refactor(stm32mp15-fdts): remove RCC secure-status

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fix(n1sdp): add numa node id for pcie controllers

If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-

fix(n1sdp): add numa node id for pcie controllers

If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-id=0 and
pcie_secondary_ctlr is assigned numa-node-id=1.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I533abdd6ea162df7b15ee04cbfc48ba7a544b91a

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fix(n1sdp): replace non-inclusive terms from dts file

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I6aa3b6dcf7c2fea18ea2d4f44a2293123ff34bdf

refactor(stm32mp15-fdts): remove timers15 node

The node is currently not used in TF-A. Remove it.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f06

refactor(stm32mp15-fdts): remove timers15 node

The node is currently not used in TF-A. Remove it.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f0689f

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refactor(stm32mp15-fdts): remove unused secure-status properties

For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED)

refactor(stm32mp15-fdts): remove unused secure-status properties

For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137

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refactor(stm32mp15-fdts): remove RCC secure-status

The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.

refactor(stm32mp15-fdts): remove RCC secure-status

The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.

[1] 812daf916c ("feat(st): update the security based on new compatible")

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6

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feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM

This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition an

feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM

This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition and the
Avenger96 baseboard like it's done in Linux and U-Boot.

Differences to stm32mp157a-avenger96.dts:
- Enable sdmmc2 for booting from eMMC
- improved clock settings like in U-Boot commit b6055945
"ARM: dts: stm32: Adjust PLL4 settings on AV96 again"
- improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74
"ARM: dts: stm32: Synchronize DDR setttings on DH SoMs"

TF-A with this new dts(i) files on this board was fully tested with
the latest OP-TEE developer setup.

Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

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feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config

Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.

Signed-off-by: Yann Gautier <yann.gautier@st.c

feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config

Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib31bed1ffe89ff221fab1884a2db729ce1e21846

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fix(stm32mp13-fdts): cleanup DT files

Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals th

fix(stm32mp13-fdts): cleanup DT files

Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals that are not used in TF-A on STM32MP13.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I0c408d29b55cb94644c92539460fc62485781223

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fix(stm32mp13-fdts): update SDMMC max frequency

On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.

fix(stm32mp13-fdts): update SDMMC max frequency

On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If4b364f53f87d4b5d276a976af486a3bf083f49b

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fix(stm32mp13-fdts): align sdmmc pins with kernel

Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordi

fix(stm32mp13-fdts): align sdmmc pins with kernel

Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordingly.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e1f3cf78794bfb7bbe53cfc7e88623c7e79855d

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