1/* 2 * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8#include "morello.dtsi" 9 10/ { 11 model = "Arm Morello Fixed Virtual Platform"; 12 13 chosen { 14 stdout-path = "serial0:115200n8"; 15 }; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 secure-firmware@ff000000 { 23 reg = <0 0xff000000 0 0x01000000>; 24 no-map; 25 }; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&CPU0>; 36 }; 37 core1 { 38 cpu = <&CPU1>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&CPU2>; 44 }; 45 core1 { 46 cpu = <&CPU3>; 47 }; 48 }; 49 }; 50 CPU0: cpu0@0 { 51 compatible = "arm,armv8"; 52 reg = <0x0 0x0>; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 clocks = <&scmi_dvfs 0>; 56 }; 57 CPU1: cpu1@100 { 58 compatible = "arm,armv8"; 59 reg = <0x0 0x100>; 60 device_type = "cpu"; 61 enable-method = "psci"; 62 clocks = <&scmi_dvfs 0>; 63 }; 64 CPU2: cpu2@10000 { 65 compatible = "arm,armv8"; 66 reg = <0x0 0x10000>; 67 device_type = "cpu"; 68 enable-method = "psci"; 69 clocks = <&scmi_dvfs 1>; 70 }; 71 CPU3: cpu3@10100 { 72 compatible = "arm,armv8"; 73 reg = <0x0 0x10100>; 74 device_type = "cpu"; 75 enable-method = "psci"; 76 clocks = <&scmi_dvfs 1>; 77 }; 78 }; 79 80 /* The first bank of memory, memory map is actually provided by UEFI. */ 81 memory@80000000 { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 device_type = "memory"; 85 /* [0x80000000-0xffffffff] */ 86 reg = <0x00000000 0x80000000 0x0 0x80000000>; 87 }; 88 89 memory@8080000000 { 90 #address-cells = <2>; 91 #size-cells = <2>; 92 device_type = "memory"; 93 /* [0x8080000000-0x83ffffffff] */ 94 reg = <0x00000080 0x80000000 0x1 0x80000000>; 95 }; 96 97 virtio_block@1c170000 { 98 compatible = "virtio,mmio"; 99 reg = <0x0 0x1c170000 0x0 0x200>; 100 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102 103 virtio_net@1c180000 { 104 compatible = "virtio,mmio"; 105 reg = <0x0 0x1c180000 0x0 0x200>; 106 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 107 }; 108 109 virtio_rng@1c190000 { 110 compatible = "virtio,mmio"; 111 reg = <0x0 0x1c190000 0x0 0x200>; 112 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 113 }; 114 115 virtio_p9@1c1a0000 { 116 compatible = "virtio,mmio"; 117 reg = <0x0 0x1c1a0000 0x0 0x200>; 118 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 ethernet@1d100000 { 122 compatible = "smsc,lan91c111"; 123 reg = <0x0 0x1d100000 0x0 0x10000>; 124 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 kmi@1c150000 { 128 compatible = "arm,pl050", "arm,primecell"; 129 reg = <0x0 0x1c150000 0x0 0x1000>; 130 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 132 clock-names = "KMIREFCLK", "apb_pclk"; 133 }; 134 135 kmi@1c160000 { 136 compatible = "arm,pl050", "arm,primecell"; 137 reg = <0x0 0x1c160000 0x0 0x1000>; 138 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 140 clock-names = "KMIREFCLK", "apb_pclk"; 141 }; 142 143 firmware { 144 scmi { 145 compatible = "arm,scmi"; 146 mbox-names = "tx", "rx"; 147 mboxes = <&mailbox 1 0 &mailbox 1 1>; 148 shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 scmi_dvfs: protocol@13 { 153 reg = <0x13>; 154 #clock-cells = <1>; 155 }; 156 }; 157 }; 158 159 bp_clock24mhz: clock24mhz { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 clock-frequency = <24000000>; 163 clock-output-names = "bp:clock24mhz"; 164 }; 165}; 166 167&gic { 168 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 169 <0x0 0x300c0000 0 0x80000>; /* GICR */ 170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 171}; 172