feat(stm32mp15-fdts): add support for prtt1x board family

Add one device tree to support a family of boards (PRTT1C, PRTT1S,
PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for
indust

feat(stm32mp15-fdts): add support for prtt1x board family

Add one device tree to support a family of boards (PRTT1C, PRTT1S,
PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for
industrial, 10BaseT1L based networks.

This change was tested with barebox 2022.12.0 bootloader and kernel
v6.2.0-rc1.

Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Change-Id: Ibab9933eadd7aa379ae0a7c7ccbfc2fbb9a44ca8

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feat(morello): add GPU DT node

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Change-Id: Ie82158aeaaf9e4bc68bc4bb91e3a9cc572b40d23

Merge "refactor(tc): update total compute gpu device node" into integration

refactor(tc): update total compute gpu device node

updated gpu clocks and added gpu simple power model node

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ia475f136bec8a569

refactor(tc): update total compute gpu device node

updated gpu clocks and added gpu simple power model node

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ia475f136bec8a569f764255eb87c212a692626dc

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feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are a

feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20

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Merge changes from topic "st_dt_update" into integration

* changes:
refactor(stm32mp15-fdts): remove unused PMIC nodes
fix(stm32mp15-fdts): use interrupts-extended for i2c2
style(stm32mp15-fdt

Merge changes from topic "st_dt_update" into integration

* changes:
refactor(stm32mp15-fdts): remove unused PMIC nodes
fix(stm32mp15-fdts): use interrupts-extended for i2c2
style(stm32mp15-fdts): remove extra spaces on vbus

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refactor(stm32mp15-fdts): remove unused PMIC nodes

The onkey and watchdog features of the PMIC are not used in TF-A for
STM32MP15 boards. Remove the nodes from DT.

Signed-off-by: Yann Gautier <yann

refactor(stm32mp15-fdts): remove unused PMIC nodes

The onkey and watchdog features of the PMIC are not used in TF-A for
STM32MP15 boards. Remove the nodes from DT.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2933e0bdc5843fcb549a817742106d9c66097869

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fix(stm32mp15-fdts): use interrupts-extended for i2c2

Update SoC DT file STM32MP151 to use interrupts-extended instead of
interrupts for i2c2. This correct a compilation warning:
build/stm32mp1/debu

fix(stm32mp15-fdts): use interrupts-extended for i2c2

Update SoC DT file STM32MP151 to use interrupts-extended instead of
interrupts for i2c2. This correct a compilation warning:
build/stm32mp1/debug/fdts/stm32mp157c-ev1-bl2.pre.dts:23.3-26:
Warning (interrupts_property): /soc/i2c@40013000:#interrupt-cells:
size is (28), expected multiple of 12

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If512807cd23c72f95e1e02b15f30d20a849d8412

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style(stm32mp15-fdts): remove extra spaces on vbus

Remove extra spaces before the closing brace of vbus_otg node in
stm32mp157c-ed1 DT file, before the vbus_sw label, and before the
closing brace of

style(stm32mp15-fdts): remove extra spaces on vbus

Remove extra spaces before the closing brace of vbus_otg node in
stm32mp157c-ed1 DT file, before the vbus_sw label, and before the
closing brace of vbus_sw node.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2e77e0a043594876551ed8d77ed3d13f6a098c81

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fix(plat/tc): increase TC_TZC_DRAM1_SIZE

Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size.
Update OP-TEE reserved memory range in DTS

Change-Id: Iad433c3c155f28860b15bde2398df6534871

fix(plat/tc): increase TC_TZC_DRAM1_SIZE

Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size.
Update OP-TEE reserved memory range in DTS

Change-Id: Iad433c3c155f28860b15bde2398df653487189dd
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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fix(tc): change the properties of optee reserved memory

make it part of the restricted dma pool to ensure it is not used for
general dma operations.

Change-Id: Ia14738de70b4d7719d7460ed8d16e727aea8

fix(tc): change the properties of optee reserved memory

make it part of the restricted dma pool to ensure it is not used for
general dma operations.

Change-Id: Ia14738de70b4d7719d7460ed8d16e727aea8d8c4
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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feat(tc): use smmu 700

Enable smmu for gpu and dpu

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I6f4cffdc835dc542904b0a15b1db9a3382b78c08

feat(rmm): add support for the 2nd DRAM bank

This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G

feat(rmm): add support for the 2nd DRAM bank

This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G"
Linux kernel command line option in fvp-base-psci-common.dsti
to allow memory layout discovery from the FVP device tree.
FVP parameter 'bp.dram_size' - size of main memory in gigabytes
documented in docs/components/realm-management-extension.rst
is changed from 2 to 4.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I174da4416ad5a8d41bf0ac89f356dba7c0cd3fe7

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refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE

The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562

refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE

The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp13-fdts): remove secure status

Remove the secure status for PKA and SAES entries.
The peripherals are used in BL2 at EL3, context will
remain secure only.

Change-Id: I79d95bc55a9afd27f29

fix(stm32mp13-fdts): remove secure status

Remove the secure status for PKA and SAES entries.
The peripherals are used in BL2 at EL3, context will
remain secure only.

Change-Id: I79d95bc55a9afd27f295249936d7bc332c777f5e
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

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feat(stm32mp1-fdts): add CoT and fuse references for authentication

Add the stm32mp1 CoT description file. Include the TRUSTED_BOARD_BOOT
entry in the platform device tree file.
Add the missing publ

feat(stm32mp1-fdts): add CoT and fuse references for authentication

Add the stm32mp1 CoT description file. Include the TRUSTED_BOARD_BOOT
entry in the platform device tree file.
Add the missing public root key reference for stm32mp15 and the
encryption key reference for stm32mp13.

Change-Id: I0ae2454979a3df6dd3e4361510317742e8fbc109
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

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Merge "fix(stm32mp13-fdts): correct PLL nodes name" into integration

Merge "feat(ethos-n)!: add support for SMMU streams" into integration

fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names

The arm,vexpress,config-bus DT binding restricts the possible (sub)node
names.
Adjust the current node names, to drop the unneeded address sp

fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names

The arm,vexpress,config-bus DT binding restricts the possible (sub)node
names.
Adjust the current node names, to drop the unneeded address specifier,
and make the node names binding compliant.

Change-Id: Ic48c6969268c960ce92c8ec3a756ed1d89e61b08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(fvp): fdts: Fix idle-states entry method

When firmware implements idle states via PSCI, the value of the DT
entry-method property must be "psci", not "arm,psci".

Fix this to make the CPU descri

fix(fvp): fdts: Fix idle-states entry method

When firmware implements idle states via PSCI, the value of the DT
entry-method property must be "psci", not "arm,psci".

Fix this to make the CPU description binding compliant.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icd1bf704d177368af9b7aab545f47e580791b8cc

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fix(fvp): fdts: fix memtimer subframe addressing

The arm,armv7-timer-mem DT binding documentation demands that the
#size-cells property should be <1> only.

Adjust the value to be <1> and drop the

fix(fvp): fdts: fix memtimer subframe addressing

The arm,armv7-timer-mem DT binding documentation demands that the
#size-cells property should be <1> only.

Adjust the value to be <1> and drop the now needless leading 0 in the
frame's reg property. Convert to #address-cell = <1> on the way.
Also adjust the interrupts property to use the proper GIC macros.

Change-Id: Ia2224663b1e6aaa7cf94af777473641de6a840d2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel

The existing DT files for the base FVP model are having some issues,
that lead to warnings reported by the device tree compiler.

Those

feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel

The existing DT files for the base FVP model are having some issues,
that lead to warnings reported by the device tree compiler.

Those (and many other issues around (updated) DT binding compliance)
were fixed in the Linux kernel tree, so let's sync those files back into
TF-A.
We cannot copy the files "as is" for now, since we rely on certain custom
properties to be added (max-pwr-lvl in the PSCI node, SDEI nodes, etc).

Merge in the changed parts of the Linux kernel DT (from Linux v6.0-rc1),
and rework the base file to allow including the motherboard.dtsi
unchanged. This should make any future update less painful.

As this also affects the FVP VE boards (Cortex-A7 and Cortex-A5), since
they share the motherboard include file, fix them up as well.

Change-Id: I4f74d05e5583747f8849e32f246f74aeec7a9c60
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(fvp): fdts: consolidate GICv2 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally ju

refactor(fvp): fdts: consolidate GICv2 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally just
the interrupt controller node that is different.
Since the GICv3 versions now use a generic DT include file (without any
GIC node), let's reuse that for the GICv2 versions of the FVP as well.
We just add a separate fvp-base-gicv2.dtsi file which describes the
GICv2 interrupt controller. Also shorten the compatible string, since
the GICv2 binding documentation does not allow the current combination.

This allows to remove the mostly redundant nodes from the GICv2 .dts
file.

Change-Id: I9018031bb611fb00ca7dbefc1bff7d40c3f05819
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(fvp): fdts: consolidate GICv3 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally ju

refactor(fvp): fdts: consolidate GICv3 base FVP DT files

The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally just
the interrupt controller node that is different.
To facilitate a unification, refactor the DT include files to explicitly
include a snippet with just the GICv3 description, and a generic base DT
file for the rest. This generic file can then be reused by the GICv2
versions later.

Since we can only have a /memreserve/ entry *before* any DT nodes, move
that line to each file, to allow including the GIC DT file separately.

Change-Id: I9ff357d3fe0ce46e280c30131aeae97a99631512
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): dts: drop 32-bit .dts files

Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and

feat(fvp): dts: drop 32-bit .dts files

Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and aarch64 does not make sense and is not needed.

Probably due to historic reasons (a Linux bug fixed in 2016 with Linux
commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a
different size between aarch64 and aarch32, even though the size of it
is solely governed by the parent's #address-cells property.

Consolidate this to be always 2, and always use two cells to describe
the CPU's MPIDR register.

This removes the last difference of the -aarch32 versions of the FVP
DT files, so just remove all of them. The respective versions without
that suffix can now be used with AArch32 DT clients as well.

Also remove the respective part in the documentation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e

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