Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "chore(tc): align core names to Arm Lumex" into integration

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "feat(tc): enable Arm SPE for TC4" into integration

feat(tc): enable Arm SPE for TC4

Enable the Arm SPE DT binding for TC4.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I9ea49046a663eecc2b97ec

feat(tc): enable Arm SPE for TC4

Enable the Arm SPE DT binding for TC4.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I9ea49046a663eecc2b97ecef9ca939575d71fdd9

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Merge "feat(tc): update CPU PMU nodes for tc4" into integration

Merge changes I105cd219,Ie870a7f3 into integration

* changes:
feat(tc): add SLC MSC nodes to TC4 DT
refactor(tc): clarify msc0 DT node

feat(tc): add SLC MSC nodes to TC4 DT

These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.

feat(tc): add SLC MSC nodes to TC4 DT

These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.

Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312

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feat(tc): update CPU PMU nodes for tc4

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU node per microarchitecture.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

feat(tc): update CPU PMU nodes for tc4

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU node per microarchitecture.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibbe8dacda695ccb45965c7f4680d4b03cffdb815

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Merge changes I10a3fc1d,I3aed6228 into integration

* changes:
fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu
fix(tc): fix SMMU streamId for tc4 gpu

Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration

* changes:
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
fix(tc): modify ethernet configuration for TC4 FP

Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration

* changes:
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
fix(tc): modify ethernet configuration for TC4 FPGA
fix(tc): modify gpio controller base addr for TC4 FPGA
fix(tc): modify DPU configuration in dts for TC4 FPGA
fix(tc): modify mmc configuration for TC4 FPGA
feat(tc): configure UART for TC4 FPGA

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fix(tc): modify ethernet configuration for TC4 FPGA

Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: I7b180c3eb90d7557d0011a25a742106f70

fix(tc): modify ethernet configuration for TC4 FPGA

Modify ethernet base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: I7b180c3eb90d7557d0011a25a742106f703cd264
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1

fix(tc): modify gpio controller base addr for TC4 FPGA

Modify gpio controller base addr for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Id4ad925d23937d302adfb3e0d4b1573e5ec717c1
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd4899459358299

fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): modify mmc configuration for TC4 FPGA

Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Sig

fix(tc): modify mmc configuration for TC4 FPGA

Modify mmc base addr and irq numbers for TC4 FPGA in dts to match
with its RoS configuration.

Change-Id: Ie8fe1f1d3aef1c020ac85db7c3b81dfad3722e2f
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu

As per GPU team, this change should be helpful to improve
the performance.

Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-b

fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu

As per GPU team, this change should be helpful to improve
the performance.

Change-Id: I10a3fc1d0ddf1ba0a17da6dc4f2a80f5fe567db6
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(tc): fix SMMU streamId for tc4 gpu

Currently used stream id 0x200 gives below fault,

[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000

fix(tc): fix SMMU streamId for tc4 gpu

Currently used stream id 0x200 gives below fault,

[ 9.547393][ C0] mali 2d000000.gpu: Unexpected Page fault in firmware address space at VA 0x0000000000000000
[ 9.547393][ C0] raw fault status: 0x400D02C0
[ 9.547393][ C0] exception type 0xC0: TRANSLATION_FAULT at level 0
[ 9.547393][ C0] access type 0x2: READ

As per the GPU team, GPU stream id is 0 on TC4-FPGA so change it.

Change-Id: I3aed62289c5b96fb850f0022ea7f5172c606eb95
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure acc

Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4

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feat(tc): add MCN PMU nodes in dts for TC4

Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zey

feat(tc): add MCN PMU nodes in dts for TC4

Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251

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Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration

Merge changes Ib1b810df,I5492bab5 into integration

* changes:
feat(tc): add dsu pmu node for TC4
feat(tc): enable DSU PMU el1 access for TC4

feat(tc): add devicetree node for AP/RSE MHU

These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are us

feat(tc): add devicetree node for AP/RSE MHU

These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are used to
communicate with RSE so keep rse mhu disabled for fpga.

Signed-off-by: Yu Shihai <yu.shihai@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib10b3da09626e5beb6d6cd87b1618a143234a5d0

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feat(tc): add dsu pmu node for TC4

Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-

feat(tc): add dsu pmu node for TC4

Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib1b810df65004987e9f3cf1bbd5deb5d211f3a17

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Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME a

Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME and SME2 options for TC4
feat(tc): add new TC4 RoS definitions
feat(tc): add system generic timer register definition for TC4
feat(tc): allow TARGET_VERSION=4
feat(tc): add MHUv3 register addresses for TC4
feat(tc): add device tree binding for TC4

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