1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46240000 /* hex */ 14#define MHU_RX_ADDR 46250000 /* hex */ 15 16#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" 17#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" 18#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" 19 20#define RSE_MHU_TX_ADDR 49020000 /* hex */ 21#define RSE_MHU_RX_ADDR 49030000 /* hex */ 22 23#define ETHERNET_ADDR 64000000 24#define ETHERNET_INT 799 25 26#if TARGET_FLAVOUR_FVP 27#define SYS_REGS_ADDR 60080000 28#define MMC_ADDR 600b0000 29#define MMC_INT_0 778 30#define MMC_INT_1 779 31#else /* TARGET_FLAVOUR_FPGA */ 32#define SYS_REGS_ADDR 1c010000 33#define MMC_ADDR 1c050000 34#define MMC_INT_0 107 35#define MMC_INT_1 108 36#endif /* TARGET_FLAVOUR_FVP */ 37 38#define RTC_ADDR 600a0000 39#define RTC_INT 777 40 41#define KMI_0_ADDR 60100000 42#define KMI_0_INT 784 43#define KMI_1_ADDR 60110000 44#define KMI_1_INT 785 45 46#define VIRTIO_BLOCK_ADDR 60020000 47#define VIRTIO_BLOCK_INT 769 48 49#if TARGET_FLAVOUR_FPGA 50#define DPU_ADDR 4000000000 51#define DPU_IRQ 579 52#endif 53 54#include "tc-common.dtsi" 55#if TARGET_FLAVOUR_FVP 56#include "tc-fvp.dtsi" 57#else 58#include "tc-fpga.dtsi" 59#endif /* TARGET_FLAVOUR_FVP */ 60#include "tc3-4-base.dtsi" 61 62/ { 63 smmu_700: iommu@3f000000 { 64 status = "okay"; 65 }; 66 67 smmu_700_dpu: iommu@4002a00000 { 68 status = "okay"; 69 }; 70 71 dp0: display@DPU_ADDR { 72 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 73 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 74 }; 75 76 gpu: gpu@2d000000 { 77 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>; 78 interrupt-names = "IRQAW"; 79 iommus = <&smmu_700 0x200>; 80 }; 81 82 dsu-pmu { 83 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 84 }; 85 86 cs-pmu@4 { 87 compatible = "arm,coresight-pmu"; 88 reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>; 89 }; 90 91 cs-pmu@5 { 92 compatible = "arm,coresight-pmu"; 93 reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>; 94 }; 95 96 cs-pmu@6 { 97 compatible = "arm,coresight-pmu"; 98 reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>; 99 }; 100 101 cs-pmu@7 { 102 compatible = "arm,coresight-pmu"; 103 reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>; 104 }; 105}; 106