1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46240000 /* hex */ 14#define MHU_RX_ADDR 46250000 /* hex */ 15 16#define LIT_CPU_PMU_COMPATIBLE "arm,c1-nano-pmu" 17#define MID_CPU_PMU_COMPATIBLE "arm,c1-pro-pmu" 18#define BIG_CPU_PMU_COMPATIBLE "arm,c1-ultra-pmu" 19 20#define RSE_MHU_TX_ADDR 49020000 /* hex */ 21#define RSE_MHU_RX_ADDR 49030000 /* hex */ 22 23#if TARGET_FLAVOUR_FVP 24#define ETHERNET_ADDR 64000000 25#define ETHERNET_INT 799 26#define SYS_REGS_ADDR 60080000 27#define MMC_ADDR 600b0000 28#define MMC_INT_0 778 29#define MMC_INT_1 779 30#else /* TARGET_FLAVOUR_FPGA */ 31#define ETHERNET_ADDR 18000000 32#define ETHERNET_INT 109 33#define SYS_REGS_ADDR 1c010000 34#define MMC_ADDR 1c050000 35#define MMC_INT_0 107 36#define MMC_INT_1 108 37#endif /* TARGET_FLAVOUR_FVP */ 38 39#define RTC_ADDR 600a0000 40#define RTC_INT 777 41 42#define KMI_0_ADDR 60100000 43#define KMI_0_INT 784 44#define KMI_1_ADDR 60110000 45#define KMI_1_INT 785 46 47#define VIRTIO_BLOCK_ADDR 60020000 48#define VIRTIO_BLOCK_INT 769 49 50#if TARGET_FLAVOUR_FPGA 51#define DPU_ADDR 4000000000 52#define DPU_IRQ 579 53#endif 54 55#include "tc-common.dtsi" 56#if TARGET_FLAVOUR_FVP 57#include "tc-fvp.dtsi" 58#else 59#include "tc-fpga.dtsi" 60#endif /* TARGET_FLAVOUR_FVP */ 61#include "tc-base.dtsi" 62 63/ { 64 spe-pmu-mid { 65 status = "okay"; 66 }; 67 68 spe-pmu-big { 69 status = "okay"; 70 }; 71 72 smmu_700: iommu@3f000000 { 73 status = "okay"; 74 }; 75 76 smmu_700_dpu: iommu@4002a00000 { 77 status = "okay"; 78 }; 79 80 dp0: display@DPU_ADDR { 81 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 82 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 83 }; 84 85 gpu: gpu@2d000000 { 86 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>; 87 interrupt-names = "IRQAW"; 88 iommus = <&smmu_700 0x0>; 89 system-coherency = <0x0>; 90 }; 91 92 dsu-pmu { 93 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 94 }; 95 96 cs-pmu@4 { 97 compatible = "arm,coresight-pmu"; 98 reg = <0x0 MCN_PMU_ADDR(4) 0x0 0xffc>; 99 }; 100 101 cs-pmu@5 { 102 compatible = "arm,coresight-pmu"; 103 reg = <0x0 MCN_PMU_ADDR(5) 0x0 0xffc>; 104 }; 105 106 cs-pmu@6 { 107 compatible = "arm,coresight-pmu"; 108 reg = <0x0 MCN_PMU_ADDR(6) 0x0 0xffc>; 109 }; 110 111 cs-pmu@7 { 112 compatible = "arm,coresight-pmu"; 113 reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>; 114 }; 115 116#if defined(TARGET_FLAVOUR_FPGA) 117 slc-msc@0 { 118 compatible = "arm,mpam-msc"; 119 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>; 120 }; 121 122 slc-msc@1 { 123 compatible = "arm,mpam-msc"; 124 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>; 125 }; 126 127 slc-msc@2 { 128 compatible = "arm,mpam-msc"; 129 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>; 130 }; 131 132 slc-msc@3 { 133 compatible = "arm,mpam-msc"; 134 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>; 135 }; 136 137 slc-msc@4 { 138 compatible = "arm,mpam-msc"; 139 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>; 140 }; 141 142 slc-msc@5 { 143 compatible = "arm,mpam-msc"; 144 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>; 145 }; 146 147 slc-msc@6 { 148 compatible = "arm,mpam-msc"; 149 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>; 150 }; 151 152 slc-msc@7 { 153 compatible = "arm,mpam-msc"; 154 reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>; 155 }; 156#endif /* TARGET_FLAVOUR_FPGA */ 157}; 158