Merge changes Iaf21883b,I523c5d57,I57164923 into integration

* changes:
fix(ufs): read and write attribute based on spec
fix(ufs): disables controller if enabled
refactor(ufs): adds a function

Merge changes Iaf21883b,I523c5d57,I57164923 into integration

* changes:
fix(ufs): read and write attribute based on spec
fix(ufs): disables controller if enabled
refactor(ufs): adds a function for fdeviceinit

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feat(smmu): configure SMMU Root interface

This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions

feat(smmu): configure SMMU Root interface

This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions originated from a non-secure or secure device upstream
to an SMMU. It re-uses the boot time GPT base address and configuration
programmed on the PE.
The root register file offset is platform dependent and has to be
supplied on a model command line.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07

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Merge changes from topic "st_clk_fix" into integration

* changes:
fix(st-clock): correct stm32_clk_parse_fdt_by_name
fix(st-clock): check _clk_stm32_get_parent return

Merge changes from topic "sb/mbedtls-2.28" into integration

* changes:
docs(prerequisites): upgrade to mbed TLS 2.28.0
build(deps): upgrade to mbed TLS 2.28.0

fix(ufs): read and write attribute based on spec

according to the spec, the response to read attr comes in the
ts.attr.value field and not in the data segment.

Signed-off-by: anans <anans@google.co

fix(ufs): read and write attribute based on spec

according to the spec, the response to read attr comes in the
ts.attr.value field and not in the data segment.

Signed-off-by: anans <anans@google.com>
Change-Id: Iaf21883bb7e364fd7c7e4bccb33359367a0cf99d

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fix(ufs): disables controller if enabled

ufs controller needs to be disabled if already enabled, without
this we noticed a crash at linkstartup during reinit

Signed-off-by: anans <anans@google.com>

fix(ufs): disables controller if enabled

ufs controller needs to be disabled if already enabled, without
this we noticed a crash at linkstartup during reinit

Signed-off-by: anans <anans@google.com>
Change-Id: I523c5d57c1d34f6404a6368ee3f364fbffd2e542

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Merge "fix(ufs): fix cache maintenance issues" into integration

build(deps): upgrade to mbed TLS 2.28.0

Upgrade to the latest and greatest 2.x release of Mbed TLS library
(i.e. v2.28.0) to take advantage of their bug fixes.

Note that the Mbed TLS project publis

build(deps): upgrade to mbed TLS 2.28.0

Upgrade to the latest and greatest 2.x release of Mbed TLS library
(i.e. v2.28.0) to take advantage of their bug fixes.

Note that the Mbed TLS project published version 3.x some time
ago. However, as this is a major release with API breakages, upgrading
to 3.x might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to mbed TLS 3.x after the v2.7
release of TF-A.

Actually, the upgrade this time simply boils down to including the new
source code module 'constant_time.c' into the firmware.

To quote mbed TLS v2.28.0 release notes [1]:

The mbedcrypto library includes a new source code module
constant_time.c, containing various functions meant to resist timing
side channel attacks. This module does not have a separate
configuration option, and functions from this module will be
included in the build as required.

As a matter of fact, if one is attempting to link TF-A against mbed
TLS v2.28.0 without the present patch, one gets some linker errors
due to missing symbols from this new module.

Apart from this, none of the items listed in mbed TLS release
notes [1] directly affect TF-A. Special note on the following one:

Fix a bug in mbedtls_gcm_starts() when the bit length of the iv
exceeds 2^32.

In TF-A, we do use mbedtls_gcm_starts() when the firmware decryption
feature is enabled with AES-GCM as the authenticated decryption
algorithm (DECRYPTION_SUPPORT=aes_gcm). However, the iv_len variable
which gets passed to mbedtls_gcm_starts() is an unsigned int, i.e. a
32-bit value which by definition is always less than 2**32. Therefore,
we are immune to this bug.

With this upgrade, the size of BL1 and BL2 binaries does not appear to
change on a standard sample test build (with trusted boot and measured
boot enabled).

[1] https://github.com/Mbed-TLS/mbedtls/releases/tag/v2.28.0

Change-Id: Icd5dbf527395e9e22c8fd6b77427188bd7237fd6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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refactor(ufs): adds a function for fdeviceinit

time taken for device init varies based on different devices,
instead of waiting for 200ms - we can poll on fdevice init
until it gets cleared, similar

refactor(ufs): adds a function for fdeviceinit

time taken for device init varies based on different devices,
instead of waiting for 200ms - we can poll on fdevice init
until it gets cleared, similar to what linux does

Change-Id: I571649231732fde0cd6d5be89b6f14fe905fcaff
Signed-off-by: anans <anans@google.com>

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refactor(ufs): delete unused variables

The result variable is not being used so it's better to delete it.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: Icae614076ce1ba7cdc86267473d59

refactor(ufs): delete unused variables

The result variable is not being used so it's better to delete it.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: Icae614076ce1ba7cdc86267473d59a8bec682f6c

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feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs

The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate overr

feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs

The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate override
* ITS: MBIST REQ error and ITS FMU ClkGate override

This patch explicitly enables them during the FMU init sequence.

Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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feat(gic600ae_fmu): disable SMID for unavailable blocks

This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safet

feat(gic600ae_fmu): disable SMID for unavailable blocks

This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safety mechanisms for GIC-600AE are enabled by default and should be
disabled for blocks that are not present on the platform to avoid
false positive RAS errors.

Change-Id: I52dc3bee9a8b49fd2e51d7ed851fdc803a48e6e3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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feat(gic600ae_fmu): introduce support for RAS error handling

The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC

feat(gic600ae_fmu): introduce support for RAS error handling

The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC makes
all necessary information available to software through Armv8.2 RAS
architecture compliant register space.

This patch introduces support to probe the FMU_ERRGSR register to find
the right error record. Once the correct record is identified, the
"handler" function queries the FMU_ERR<m>STATUS register to further
identify the block ID, safety mechanism and the architecturally defined
primary error code. The description of the error is displayed on the
console to simplify debug.

Change-Id: I7e543664b74457afee2da250549f4c3d9beb1a03
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(st-clock): correct stm32_clk_parse_fdt_by_name

The fdt_getprop() function sets the length to -1 if the property is not
found. We should then not use it later in stm32_clk_parse_fdt_by_name()
in

fix(st-clock): correct stm32_clk_parse_fdt_by_name

The fdt_getprop() function sets the length to -1 if the property is not
found. We should then not use it later in stm32_clk_parse_fdt_by_name()
in that case. Directly set *nb to 0U and return 0 if the property is not
found.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I19c5c953f392cdc768e0b1f3f240fc99a73a049c

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fix(st-clock): check _clk_stm32_get_parent return

This issue was found by Coverity (CID 376885). The _clk_stm32_get_parent()
return shouldn't be negative. Return the error in this case.

Signed-off-

fix(st-clock): check _clk_stm32_get_parent return

This issue was found by Coverity (CID 376885). The _clk_stm32_get_parent()
return shouldn't be negative. Return the error in this case.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I91eff7e99fcdac9a258100b163fd9b040a9bd2c0

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Merge changes I84e257b3,I1317e482 into integration

* changes:
fix(layerscape): fix coverity issue
fix(nxp-ddr): fix coverity issue

Merge "fix(scmi): use same type for message_id" into integration

fix(nxp-ddr): fix coverity issue

Check return value of mmap_add_dynamic_region().

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1317e4822f3da329185d54005f08047872b5cdce

Merge changes from topics "ls1088a", "ls1088a-prepare" into integration

* changes:
docs(layerscape): add ls1088a soc and board support
feat(ls1088aqds): add ls1088aqds board support
feat(ls108

Merge changes from topics "ls1088a", "ls1088a-prepare" into integration

* changes:
docs(layerscape): add ls1088a soc and board support
feat(ls1088aqds): add ls1088aqds board support
feat(ls1088ardb): add ls1088ardb board support
feat(ls1088a): add new SoC platform ls1088a
build(changelog): add new scopes for ls1088a
feat(bl2): add support to separate no-loadable sections
refactor(layerscape): refine comparison of inerconnection
feat(layerscape): add soc helper macro definition for chassis 3
feat(nxp-gic): add some macros definition for gicv3
feat(layerscape): add CHASSIS 3 support for tbbr
feat(layerscape): define more chassis 3 hardware address
feat(nxp-crypto): add chassis 3 support
feat(nxp-dcfg): add Chassis 3 support
feat(lx2): enable DDR erratas for lx2 platforms
feat(layerscape): print DDR errata information
feat(nxp-ddr): add workaround for errata A050958
feat(layerscape): add new soc errata a010539 support
feat(layerscape): add new soc errata a009660 support
feat(nxp-ddr): add rawcard 1F support
fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
fix(nxp-tools): fix create_pbl print log
build(changelog): add new scopes for NXP driver

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fix(fwu): rename is_fwu_initialized

The variable is_fwu_initialized was initialized after
plat_fwu_set_images_source() is called.
But some functions called by plat_fwu_set_images_source() for STM32M

fix(fwu): rename is_fwu_initialized

The variable is_fwu_initialized was initialized after
plat_fwu_set_images_source() is called.
But some functions called by plat_fwu_set_images_source() for STM32MP1
implementation expect is_fwu_initialized is set to true with asserts.
Rename is_fwu_initialized to is_metadata_initialized, and set it before
plat_fwu_set_images_source() is called.

Change-Id: I17c6ee6293dfa55385b0c859db442647f0bebaed
Signed-off-by: Sebastien Pasdeloup <sebastien.pasdeloup-ext@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(nxp-dcfg): add Chassis 3 support

Add support for Chassis 3.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799

feat(nxp-dcfg): add Chassis 3 support

Add support for Chassis 3.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799ae173aa23a

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feat(nxp-ddr): add workaround for errata A050958

Set the receiver gain to max value to recover
cold temp marginality issue for phy-gen2

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-b

feat(nxp-ddr): add workaround for errata A050958

Set the receiver gain to max value to recover
cold temp marginality issue for phy-gen2

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If639fa3ed404cf6e1b8abcc2b7137db1fdd0b2c2

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feat(nxp-ddr): add rawcard 1F support

New UDIMM 18ADF2G72AZ-2G6E1 has raw card ID = 0x1F

Also, changing mask for raw card ID from - 0x8f -> 0x9f

Changing the mask need the raw card to changed from

feat(nxp-ddr): add rawcard 1F support

New UDIMM 18ADF2G72AZ-2G6E1 has raw card ID = 0x1F

Also, changing mask for raw card ID from - 0x8f -> 0x9f

Changing the mask need the raw card to changed from 0x0f -> 0x1f

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iee8e732ebc5e09cdca6917be608f1597c7edd9f9

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Merge changes from topic "stm32mp13" into integration

* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(s

Merge changes from topic "stm32mp13" into integration

* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(stm32mp1-fdts): add DDR support for STM32MP13
feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
feat(stm32mp1): updates for STM32MP13 device tree compilation
feat(stm32mp1-fdts): add DT files for STM32MP13
feat(dt-bindings): add TZC400 bindings for STM32MP13
feat(stm32mp1): add "Boot mode" management for STM32MP13
feat(stm32mp1): manage HSLV on STM32MP13
feat(stm32mp1): add sdmmc compatible in platform define
feat(st-sdmmc2): allow compatible to be defined in platform code
feat(stm32mp1): update IO compensation on STM32MP13
feat(stm32mp1): call pmic_voltages_init() in platform init
feat(st-pmic): add pmic_voltages_init() function
feat(stm32mp1): update CFG0 OTP for STM32MP13
feat(stm32mp1): usb descriptor update for STM32MP13
feat(st-clock): add clock driver for STM32MP13
feat(dt-bindings): add bindings for STM32MP13
feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
feat(stm32mp1): use only one filter for TZC400 on STM32MP13
feat(stm32mp1): add a second fixed regulator
feat(stm32mp1): adaptations for STM32MP13 image header
feat(stm32mp1): update boot API for header v2.0
feat(stm32mp1): update IP addresses for STM32MP13
feat(stm32mp1): add part numbers for STM32MP13
feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
feat(stm32mp1): remove unsupported features on STM32MP13
feat(stm32mp1): update memory mapping for STM32MP13
feat(stm32mp1): introduce new flag for STM32MP13
feat(st): update stm32image tool for header v2

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feat(st-sdmmc2): allow compatible to be defined in platform code

Put DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not
defined in platform code.

Change-Id: I611baaf1fc622d33e655ee

feat(st-sdmmc2): allow compatible to be defined in platform code

Put DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not
defined in platform code.

Change-Id: I611baaf1fc622d33e655ee2c78d9c287baaa6a67
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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